Package envi :: Package archs :: Package thumb16 :: Module disasm
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Module disasm

source code

Classes [hide private]
  simpleops
  ThumbOpcode
  Thumb16Disasm
Functions [hide private]
 
shmaskval(value, shval, mask) source code
 
d1_rm4_rd3(va, value) source code
 
rm_rn_rt(va, value) source code
 
imm54_rn_rt(va, value) source code
 
imm55_rn_rt(va, value) source code
 
imm56_rn_rt(va, value) source code
 
rd_sp_imm8(va, value) source code
 
rd_pc_imm8(va, value) source code
 
rt_pc_imm8(va, value) source code
 
bl_imm23(va, val, val2) source code
 
pc_imm11(va, value) source code
 
pc_imm8(va, value) source code
 
ldmia(va, value) source code
 
sp_sp_imm7(va, value) source code
 
rm_reglist(va, value) source code
 
reglist(va, value) source code
 
imm5_rm_rd(va, value) source code
 
i_imm5_rn(va, value) source code
 
ldm16(va, value) source code
 
thumb32(va, val, val2) source code
 
is_thumb32(val)
Take a 16 bit integer (opcode) value and determine if it is really the first 16 bits of a 32 bit instruction.
source code
Variables [hide private]
  O_REG = 0
  O_IMM = 1
  O_OFF = 2
  OperType = ArmRegOper, ArmImmOper, ArmPcOffsetOper,
  rm_rn_rd = simpleops((O_REG, 0, 0x7), (O_REG, 3, 0x7), (O_REG,...
  imm3_rn_rd = simpleops((O_REG, 0, 0x7), (O_REG, 3, 0x7), (O_IM...
  imm8_rd = simpleops((O_REG, 8, 0x7), (O_IMM, 0, 0xff))
  rm_rd = simpleops((O_REG, 0, 0x7), (O_REG, 3, 0x7))
  rn_rdm = simpleops((O_REG, 0, 0x7), (O_REG, 3, 0x7))
  rm_rdn = simpleops((O_REG, 0, 0x7), (O_REG, 3, 0x7))
  rm_rd_imm0 = simpleops((O_REG, 0, 0x7), (O_REG, 3, 0x7), (O_IM...
  rm4_shift3 = simpleops((O_REG, 3, 0xf))
  imm8 = simpleops((O_IMM, 8, 0xff))
  sh4_imm1 = simpleops((O_IMM, 3, 0x1))
  thumb_base = [('00000', (0, 'lsl', imm5_rm_rd, 0)), ('00001', ...
  thumb1_extension = [('11100', (INS_B, 'b', pc_imm11, 0)), ('11...
  thumb2_extension = [('11100', (85, 'ldm', ldm16, 0)), ('11101'...
('111010000000', (85,'srs', srs_32, 0)), ('111010000001', (85,'rfe', rfe_32, 0)), ('111010000010', (85,'srs', srs_32, 0)), ('111010000011', (85,'rfe', rfe_32, 0)),
  thumb_table = list(thumb_base)
  thumb2_table = list(thumb_base)
  ttree = e_btree.BinaryTree()
  thumb32mask = binary('11111')
  thumb32min = binary('11100')
Variables Details [hide private]

rm_rn_rd

Value:
simpleops((O_REG, 0, 0x7), (O_REG, 3, 0x7), (O_REG, 6, 0x7))

imm3_rn_rd

Value:
simpleops((O_REG, 0, 0x7), (O_REG, 3, 0x7), (O_IMM, 6, 0x7))

rm_rd_imm0

Value:
simpleops((O_REG, 0, 0x7), (O_REG, 3, 0x7), (O_IMM, 0, 0))

thumb_base

Value:
[('00000', (0, 'lsl', imm5_rm_rd, 0)), ('00001', (1, 'lsr', imm5_rm_rd\
, 0)), ('00010', (2, 'asr', imm5_rm_rd, 0)), ('0001100', (INS_ADD, 'ad\
d', rm_rn_rd, 0)), ('0001101', (INS_SUB, 'sub', rm_rn_rd, 0)), ('00011\
10', (INS_ADD, 'add', imm3_rn_rd, 0)), ('0001111', (INS_SUB, 'sub', im\
m3_rn_rd, 0)), ('00100', (7, 'mov', imm8_rd, 0)), ('00101', (8, 'cmp',\
 imm8_rd, 0)), ('00110', (INS_ADD, 'add', imm8_rd, 0)), ('00111', (INS\
_SUB, 'sub', imm8_rd, 0)), ('0100000000', (11, 'and', rm_rdn, 0)), ('0\
100000001', (12, 'eor', rm_rdn, 0)), ('0100000010', (13, 'lsl', rm_rdn\
...

thumb1_extension

Value:
[('11100', (INS_B, 'b', pc_imm11, 0)), ('1111', (INS_BL, 'bl', bl_imm2\
3, IF_THUMB32)),]

thumb2_extension

('111010000000', (85,'srs', srs_32, 0)), ('111010000001', (85,'rfe', rfe_32, 0)), ('111010000010', (85,'srs', srs_32, 0)), ('111010000011', (85,'rfe', rfe_32, 0)),

('111010001000', (85,'stm', ldm32, 0)), ('111010001001', (85,'ldm', ldm32, 0)), ('111010001010', (85,'stm', ldm32, 0)), ('111010001011', (85,'ldm', ldm32, 0)),

('111010010000', (85,'srs', srs_32, 0)), ('111010010001', (85,'rfe', rfe_32, 0)), ('111010010010', (85,'srs', srs_32, 0)), ('111010010011', (85,'rfe', rfe_32, 0)),

('111010011000', (85,'stm', ldm16, 0)), ('111010011001', (85,'ldm', ldm16, 0)), ('111010011010', (85,'stm', ldm16, 0)), ('111010011011', (85,'ldm', ldm16, 0)),

]

Value:
[('11100', (85, 'ldm', ldm16, 0)), ('11101', (86, 'blah32', thumb32, 0\
)), ('1111', (86, 'blah32', thumb32, 0)),]