Package envi :: Package archs :: Package arm :: Module emu
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Module emu

source code

The initial arm module.

Classes [hide private]
  ArmArchitectureProcedureCall
Implement calling conventions for your arch.
  CoProcEmulator
  ArmEmulator
Variables [hide private]
  aapcs = ArmArchitectureProcedureCall()
  opcode_dist = [('and', 4083), ('stm', 1120), ('ldr', 1064), ('...
A2.3.1 Writing to the PC In ARMv7, many data-processing instructions can write to the PC.
Variables Details [hide private]

opcode_dist


A2.3.1 Writing to the PC
    In ARMv7, many data-processing instructions can write to the PC. Writes to the PC are handled as follows:
        * In Thumb state, the following 16-bit Thumb instruction encodings branch to the value written to the PC:
            - encoding T2 of ADD (register, Thumb) on page A8-308
            - encoding T1 of MOV (register, Thumb) on page A8-484.
            The value written to the PC is forced to be halfword-aligned by ignoring its least significant bit, treating that
            bit as being 0.
        * The B, BL, CBNZ, CBZ, CHKA, HB, HBL, HBLP, HBP, TBB, and TBH instructions remain in the same instruction set state
            and branch to the value written to the PC.
            The definition of each of these instructions ensures that the value written to the PC is correctly aligned for
            the current instruction set state.
        * The BLX (immediate) instruction switches between ARM and Thumb states and branches to the value written
            to the PC. Its definition ensures that the value written to the PC is correctly aligned for the new instruction
            set state.
        * The following instructions write a value to the PC, treating that value as an interworking address to branch
            to, with low-order bits that determine the new instruction set state:
                - BLX (register), BX, and BXJ
                - LDR instructions with <Rt> equal to the PC
                - POP and all forms of LDM except LDM (exception return), when the register list includes the PC
                - in ARM state only, ADC, ADD, ADR, AND, ASR (immediate), BIC, EOR, LSL (immediate), LSR (immediate), MOV,
                    MVN, ORR, ROR (immediate), RRX, RSB, RSC, SBC, and SUB instructions with <Rd> equal to the PC and without
                    flag-setting specified.
            For details of how an interworking address specifies the new instruction set state and instruction address, see
            Pseudocode details of operations on ARM core registers on page A2-47.
            Note
                - The register-shifted register instructions, that are available only in the ARM instruction set and are
                    summarized inData-processing (register-shifted register) on page A5-196, cannot write to the PC.
                - The LDR, POP, and LDM instructions first have interworking branch behavior in ARMv5T.
                - The instructions listed as having interworking branch behavior in ARM state only first have this
                    behavior in ARMv7.
                In the cases where later versions of the architecture introduce interworking branch behavior, the behavior in
                earlier architecture versions is a branch that remains in the same instruction set state. For more information,
                see:
                    - Interworking on page AppxL-2453, for ARMv6
                    - Interworking on page AppxO-2539, for ARMv5 and ARMv4.
        * Some instructions are treated as exception return instructions, and write both the PC and the CPSR. For more
            information, including which instructions are exception return instructions, see Exception return on
            page B1-1191.
        * Some instructions cause an exception, and the exception handler address is written to the PC as part of the
            exception entry. Similarly, in ThumbEE state, an instruction that fails its null check causes the address of the
            null check handler to be written to the PC, see Null checking on page A9-1111.

Value:
[('and', 4083), ('stm', 1120), ('ldr', 1064), ('add', 917), ('stc', 85\
9), ('str', 770), ('bl', 725), ('ldm', 641), ('b', 472), ('ldc', 469),\
 ('tst', 419), ('rsb', 196), ('eor', 180), ('mul', 159), ('swi', 128),\
 ('sub', 110), ('adc', 96), ('cdp', 74), ('orr', 66), ('cmn', 59), ('m\
cr', 55), ('stc2', 54), ('ldc2', 52), ('mrc', 49), ('mvn', 47), ('rsc'\
, 46), ('teq', 45), ('cmp', 41), ('sbc', 40), ('mov', 35), ('bic', 34)\
, ('mcr2', 29), ('mrc2', 28), ('swp', 28), ('mcrr', 21), ('mrrc', 20),\
 ('usada8', 20), ('qadd', 13), ('mrrc2', 10), ('add16', 9), ('mla', 9)\
...