Package envi :: Package archs :: Package arm :: Module disasm
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Module disasm

source code

Classes [hide private]
  ArmOpcode
  ArmOperand
  ArmRegOper
register operand.
  ArmRegShiftRegOper
register shift operand.
  ArmRegShiftImmOper
register shift immediate operand.
  ArmImmOper
register operand.
  ArmScaledOffsetOper
scaled offset operand.
  ArmRegOffsetOper
register offset operand.
  ArmImmOffsetOper
immediate offset operand.
  ArmPcOffsetOper
PC + imm_offset
  ArmPgmStatRegOper
  ArmPgmStatFlagsOper
  ArmEndianOper
  ArmRegListOper
  ArmPSRFlagsOper
  ArmCoprocOpcodeOper
  ArmCoprocOper
  ArmCoprocRegOper
  ArmModeOper
  ArmDisasm
Functions [hide private]
 
chopmul(opcode) source code
 
addrToName(mcanv, va) source code
 
sh_lsl(num, shval) source code
 
sh_lsr(num, shval) source code
 
sh_asr(num, shval) source code
 
sh_ror(num, shval) source code
 
sh_rrx(num, shval, emu=None) source code
 
dpbase(opval)
Parse and return opcode,sflag,Rn,Rd for a standard dataprocessing instruction.
source code
 
p_dp_imm_shift(opval, va) source code
 
p_misc(opval, va) source code
 
p_misc1(opval, va) source code
 
p_extra_load_store(opval, va) source code
 
p_dp_reg_shift(opval, va) source code
 
p_mult(opval, va) source code
 
p_dp_imm(opval, va) source code
 
p_undef(opval, va) source code
 
p_mov_imm_stat(opval, va) source code
 
p_load_imm_off(opval, va) source code
 
p_load_reg_off(opval, va) source code
 
p_media(opval, va)
27:20, 7:4
source code
 
p_media_parallel(opval, va) source code
 
p_media_pack_sat_rev_extend(opval, va) source code
 
p_media_smul(opval, va) source code
 
p_media_usada(opval, va) source code
 
p_arch_undef(opval, va) source code
 
p_load_mult(opval, va) source code
 
p_branch(opval, va) source code
 
p_coproc_load(opval, va) source code
 
p_coproc_dbl_reg_xfer(opval, va) source code
 
p_coproc_dp(opval, va) source code
 
p_coproc_reg_xfer(opval, va) source code
 
p_swint(opval, va) source code
 
p_uncond(opval, va) source code
Variables [hide private]
  iencmul_codes = {binary("000000001001"):("mul", (0, 4, 2), 0),...
  shifters = sh_lsl, sh_lsr, sh_asr, sh_ror, sh_rrx,
  dp_mnem = "and", "eor", "sub", "rsb", "add", "adc", "sbc", "rs...
  dp_noRn = 13, 15
  dp_noRd = 8, 9, 10, 11
  dp_ADR = 2, 4,
  qop_mnem = 'qadd', 'qsub', 'qdadd', 'qdsub'
  smla_mnem = 'smlabb', 'smlabt', 'smlatb', 'smlatt',
  smlal_mnem = 'smlalbb', 'smlalbt', 'smlaltb', 'smlaltt',
  smul_mnem = 'smulbb', 'smulbt', 'smultb', 'smultt',
  smlaw_mnem = 'smlawb', 'smlawt',
  smulw_mnem = 'smulwb', 'smulwt',
  swap_mnem = "swp", "swpb",
  strex_mnem = "strex", "ldrex",
  strh_mnem = "str", IF_H, ("ldr", IF_H),
  ldrs_mnem = "ldr", IF_S | IF_B, ("ldr", IF_S | IF_H),
  ldrd_mnem = "ldr", IF_D, ("str", IF_D),
  multfail = None, None, None,
  ldr_mnem = "str", "ldr"
  tsizes = 4, 1,
  par_suffixes = "add16", "addsubx", "subaddx", "sub16", "add8",...
  par_prefixes = "", "s", "q", "sh", "", "u", "uq", "uh"
  parallel_mnem = tuple(parallel_mnem)
  xtnd_suffixes = "xtab16", "xtab", "xtah", "xtb16", "xtb", "xth",
  xtnd_prefixes = "s", "u"
  xtnd_mnem = tuple(xtnd_mnem)
  pkh_mnem = 'pkhbt', 'pkhtb',
  sat_mnem = 'ssat', 'usat'
  sat16_mnem = 'ssat16', 'usat16'
  rev_mnem = 'rev', 'rev16', None, 'revsh',
  ldm_mnem = "stm", "ldm"
  b_mnem = "b", "bl",
  ldc_mnem = "stc", "ldc",
  mcrr_mnem = "mcrr", "mrrc"
  cdp_mnem = ["cdp" for x in range(15)]
  mcr_mnem = "mcr", "mrc"
  cps_mnem = "cps", "cps FAIL-bad encoding", "cpsie", "cpsid"
  mcrr2_mnem = "mcrr2", "mrrc2"
  ldc2_mnem = "stc2", "ldc2",
  mcr2_mnem = "mcr2", "mrc2"
  ienc_parsers_tmp = [None for x in range(21)]
  ienc_parsers = tuple(ienc_parsers_tmp)
  s_0_table = 0b00000001100100000000000000010000, 0b000000010000...
  s_1_table = 0b00001111101100000000000000000000, 0b000000110010...
  s_3_table = 0b00000001111100000000000011110000, 0b000000011111...
  s_6_table = 0b00001111111000000000000000000000, 0b000011000100...
  s_7_table = 0b00000001000000000000000000000000, 0b000000010000...
  inittable = [(None, s_0_table), (None, s_1_table), (IENC_LOAD_...
  endian_names = "le", "be"
  psrs = "CPSR", "SPSR", 'inval', 'inval', 'inval', 'inval', 'in...
  aif_flags = None, 'f', 'i', 'if', 'a', 'af', 'ai', 'aif'
  ENDIAN_LSB = 0
  ENDIAN_MSB = 1
Variables Details [hide private]

iencmul_codes

Value:
{binary("000000001001"):("mul", (0, 4, 2), 0), binary("000000011001"):\
("mul", (0, 4, 2), IF_PSR_S), binary("000000101001"):("mla", (0, 4, 2,\
 1), 0), binary("000000111001"):("mla", (0, 4, 2, 1), IF_PSR_S), binar\
y("000001001001"):("umaal", (1, 0, 4, 2), 0), binary("000010001001"):(\
"umull", (1, 0, 4, 2), 0), binary("000010011001"):("umull", (1, 0, 4, \
2), IF_PSR_S), binary("000010101001"):("umlal", (1, 0, 4, 2), 0), bina\
ry("000010111001"):("umlal", (1, 0, 4, 2), IF_PSR_S), binary("00001100\
1001"):("smull", (1, 0, 4, 2), 0), binary("000011011001"):("smull", (1\
...

dp_mnem

Value:
"and", "eor", "sub", "rsb", "add", "adc", "sbc", "rsc", "tst", "teq", \
"cmp", "cmn", "orr", "mov", "bic", "mvn", "adr"

par_suffixes

Value:
"add16", "addsubx", "subaddx", "sub16", "add8", "sub8", "", ""

s_0_table

Value:
0b00000001100100000000000000010000, 0b00000001000000000000000000000000\
, IENC_MISC, (0b00000000000000000000000000010000, 0b000000000000000000\
00000000000000, IENC_DP_IMM_SHIFT), (0b0000000110010000000000001001000\
0, 0b00000001000000000000000000010000, IENC_MISC1), (0b000000010000000\
00000000011110000, 0b00000000000000000000000010010000, IENC_MULT), (0b\
00000001001000000000000010010000, 0b00000001001000000000000010010000, \
IENC_EXTRA_LOAD), (0b00000000000000000000000010010000, 0b0000000000000\
0000000000010010000, IENC_EXTRA_LOAD), (0b0000000000000000000000001001\
...

s_1_table

Value:
0b00001111101100000000000000000000, 0b00000011001000000000000000000000\
, IENC_MOV_IMM_STAT, (0b00000001100110000000000000000000, 0b0000000100\
0000000000000000000000, IENC_UNDEF), (0, 0, IENC_DP_IMM),

s_3_table

Value:
0b00000001111100000000000011110000, 0b00000001111100000000000011110000\
, IENC_ARCH_UNDEF, (0b00000000000000000000000000010000, 0b000000000000\
00000000000000010000, IENC_MEDIA), (0, 0, IENC_LOAD_REG_OFF),

s_6_table

Value:
0b00001111111000000000000000000000, 0b00001100010000000000000000000000\
, IENC_COPROC_RREG_XFER, (0b00001110000000000000000000000000, 0b000011\
00000000000000000000000000, IENC_COPROC_LOAD),

s_7_table

Value:
0b00000001000000000000000000000000, 0b00000001000000000000000000000000\
, IENC_SWINT, (0b00000001000000000000000000010000, 0b00000000000000000\
000000000010000, IENC_COPROC_REG_XFER), (0, 0, IENC_COPROC_DP),

inittable

Value:
[(None, s_0_table), (None, s_1_table), (IENC_LOAD_IMM_OFF, None), (Non\
e, s_3_table), (IENC_LOAD_MULT, None), (IENC_BRANCH, None), (None, s_6\
_table), (None, s_7_table), (IENC_UNCOND, None),]

psrs

Value:
"CPSR", "SPSR", 'inval', 'inval', 'inval', 'inval', 'inval', 'inval',