Package envi :: Package archs :: Package arm :: Module const
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Module const

source code

Functions [hide private]
 
instrenc(encoding, index) source code
Variables [hide private]
  MODE_ARM = 0
  MODE_THUMB = 1
  MODE_JAZELLE = 2
  IF_PSR_S = 1 << 32
  IF_B = 1 << 33
  IF_H = 1 << 35
  IF_S = 1 << 36
  IF_D = 1 << 37
  IF_L = 1 << 38
  IF_T = 1 << 39
  IF_W = 1 << 40
  IF_UM = 1 << 41
  IF_DAIB_SHFT = 56
  IF_DAIB_MASK = 7 <<(IF_DAIB_SHFT-1)
  IF_DA = 1 <<(IF_DAIB_SHFT-1)
  IF_IA = 3 <<(IF_DAIB_SHFT-1)
  IF_DB = 5 <<(IF_DAIB_SHFT-1)
  IF_IB = 7 <<(IF_DAIB_SHFT-1)
  IF_DAIB_B = 5 <<(IF_DAIB_SHFT-1)
  IF_DAIB_I = 3 <<(IF_DAIB_SHFT-1)
  IF_THUMB32 = 1 << 50
  OF_W = 1 << 8
  OF_UM = 1 << 9
  OSZFMT_BYTE = "B"
  OSZFMT_HWORD = "<H"
  OSZFMT_WORD = "<L"
  OSZ_BYTE = 1
  OSZ_HWORD = 2
  OSZ_WORD = 4
  fmts = [None, OSZ_BYTE, OSZ_HWORD, None, OSZ_WORD]
  COND_EQ = 0x0
  COND_NE = 0x1
  COND_CS = 0x2
  COND_CC = 0x3
  COND_MI = 0x4
  COND_PL = 0x5
  COND_VS = 0x6
  COND_VC = 0x7
  COND_HI = 0x8
  COND_LO = 0x9
  COND_GE = 0xA
  COND_LT = 0xB
  COND_GT = 0xC
  COND_LE = 0xD
  COND_AL = 0xE
  COND_EXTENDED = 0xF
  cond_codes = {COND_EQ: "eq", COND_NE: "ne", COND_CS: "cs", CON...
  PM_usr = 0b10000
  PM_fiq = 0b10001
  PM_irq = 0b10010
  PM_svc = 0b10011
  PM_abt = 0b10111
  PM_und = 0b11011
  PM_sys = 0b11111
  REG_OFFSET_USR = 17*(PM_usr & 0xf)
  REG_OFFSET_FIQ = 17*(PM_fiq & 0xf)
  REG_OFFSET_IRQ = 17*(PM_irq & 0xf)
  REG_OFFSET_SVC = 17*(PM_svc & 0xf)
  REG_OFFSET_ABT = 17*(PM_abt & 0xf)
  REG_OFFSET_UND = 17*(PM_und & 0xf)
  REG_OFFSET_SYS = 17*(PM_sys & 0xf)
  REG_OFFSET_CPSR = 16
  REG_SPSR_usr = REG_OFFSET_USR+ 16
  REG_SPSR_fiq = REG_OFFSET_FIQ+ 16
  REG_SPSR_irq = REG_OFFSET_IRQ+ 16
  REG_SPSR_svc = REG_OFFSET_SVC+ 16
  REG_SPSR_abt = REG_OFFSET_ABT+ 16
  REG_SPSR_und = REG_OFFSET_UND+ 16
  REG_SPSR_sys = REG_OFFSET_SYS+ 16
  REG_PC = 0xf
  REG_SP = 0xd
  REG_BP = None
hash(x)
  REG_CPSR = 16
  REG_FLAGS = 16
  proc_modes = {PM_usr:("User Processor Mode", "usr", "Normal pr...
  PM_LNAME = 0
  PM_SNAME = 1
  PM_DESC = 2
  PM_REGOFF = 3
  PM_BANKED = 4
  PM_SPSR = 5
  INST_ENC_DP_IMM = 0
  INST_ENC_MISC = 1
  IENC_DP_IMM_SHIFT = 0
  IENC_MISC = 1
  IENC_MISC1 = 2
  IENC_DP_REG_SHIFT = 3
  IENC_MULT = 4
  IENC_UNDEF = 5
  IENC_MOV_IMM_STAT = 6
  IENC_DP_IMM = 7
  IENC_LOAD_IMM_OFF = 8
  IENC_LOAD_REG_OFF = 9
  IENC_ARCH_UNDEF = 10
  IENC_MEDIA = 11
  IENC_LOAD_MULT = 12
  IENC_BRANCH = 13
  IENC_COPROC_RREG_XFER = 14
  IENC_COPROC_LOAD = 15
  IENC_COPROC_DP = 16
  IENC_COPROC_REG_XFER = 17
  IENC_SWINT = 18
  IENC_UNCOND = 19
  IENC_EXTRA_LOAD = 20
  IENC_MEDIA_PARALLEL = IENC_MEDIA << 8+ 1 << 8
  IENC_MEDIA_SAT = IENC_MEDIA << 8+ 2 << 8
  IENC_MEDIA_REV = IENC_MEDIA << 8+ 3 << 8
  IENC_MEDIA_SEL = IENC_MEDIA << 8+ 4 << 8
  IENC_MEDIA_USAD8 = IENC_MEDIA << 8+ 5 << 8
  IENC_MEDIA_USADA8 = IENC_MEDIA << 8+ 6 << 8
  IENC_MEDIA_EXTEND = IENC_MEDIA << 8+ 7 << 8
  IENC_MEDIA_PACK = IENC_MEDIA << 8+ 8 << 8
  IENC_UNCOND_CPS = IENC_UNCOND << 8+ 1 << 8
  IENC_UNCOND_SETEND = IENC_UNCOND << 8+ 2 << 8
  IENC_UNCOND_PLD = IENC_UNCOND << 8+ 3 << 8
  IENC_UNCOND_BLX = IENC_UNCOND << 8+ 4 << 8
  IENC_UNCOND_RFE = IENC_UNCOND << 8+ 5 << 8
  S_LSL = 0
  S_LSR = 1
  S_ASR = 2
  S_ROR = 3
  S_RRX = 4
  shift_names = "lsl", "lsr", "asr", "ror", "rrx"
  SOT_REG = 0
  SOT_IMM = 1
  daib = "da", "ia", "db", "ib"
  INS_EOR = IENC_DP_IMM_SHIFT << 16+ 1
  INS_SUB = IENC_DP_IMM_SHIFT << 16+ 2
  INS_RSB = IENC_DP_IMM_SHIFT << 16+ 3
  INS_ADD = IENC_DP_IMM_SHIFT << 16+ 4
  INS_ADC = IENC_DP_IMM_SHIFT << 16+ 5
  INS_SBC = IENC_DP_IMM_SHIFT << 16+ 6
  INS_RSC = IENC_DP_IMM_SHIFT << 16+ 7
  INS_TST = IENC_DP_IMM_SHIFT << 16+ 8
  INS_TEQ = IENC_DP_IMM_SHIFT << 16+ 9
  INS_CMP = IENC_DP_IMM_SHIFT << 16+ 10
  INS_CMN = IENC_DP_IMM_SHIFT << 16+ 11
  INS_ORR = IENC_DP_IMM_SHIFT << 16+ 12
  INS_MOV = IENC_DP_IMM_SHIFT << 16+ 13
  INS_BIC = IENC_DP_IMM_SHIFT << 16+ 14
  INS_MVN = IENC_DP_IMM_SHIFT << 16+ 15
  INS_B = instrenc(IENC_BRANCH, 0)
  INS_BL = instrenc(IENC_BRANCH, 1)
  INS_BCC = instrenc(IENC_BRANCH, 2)
  INS_BX = instrenc(IENC_MISC, 3)
  INS_BXJ = instrenc(IENC_MISC, 5)
  INS_BLX = IENC_UNCOND << 8+ 4 << 8
  INS_SWI = 18
  no_update_Rd = INS_TST, INS_TEQ, INS_CMP, INS_CMN,
Variables Details [hide private]

cond_codes

Value:
{COND_EQ: "eq", COND_NE: "ne", COND_CS: "cs", COND_CC: "cc", COND_MI: \
"mi", COND_PL: "pl", COND_VS: "vs", COND_VC: "vc", COND_HI: "hi", COND\
_LO: "lo", COND_GE: "ge", COND_LT: "lt", COND_GT: "gt", COND_LE: "le",\
 COND_AL: "", COND_EXTENDED: "2",}

proc_modes

Value:
{PM_usr:("User Processor Mode", "usr", "Normal program execution mode"\
, REG_OFFSET_USR, 15, REG_SPSR_usr), PM_fiq:("FIQ Processor Mode", "fi\
q", "Supports a high-speed data transfer or channel process", REG_OFFS\
ET_FIQ, 8, REG_SPSR_fiq), PM_irq:("IRQ Processor Mode", "irq", "Used f\
or general-purpose interrupt handling", REG_OFFSET_IRQ, 13, REG_SPSR_i\
rq), PM_svc:("Supervisor Processor Mode", "svc", "A protected mode for\
 the operating system", REG_OFFSET_SVC, 13, REG_SPSR_svc), PM_abt:("Ab\
ort Processor Mode", "abt", "Implements virtual memory and/or memory p\
...