Package envi :: Package archs :: Package amd64 :: Module opcode64
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Module opcode64

source code

Variables [hide private]
  tbl32_Main = [(0, INS_ADD, ADDRMETH_E | OPTYPE_b | OP_W, ADDRM...
(optable, optype, operand 0, operand 1, operand 2, CPU required, "opcodename", op0Register, op1Register, op2Register)
  tbl32_0F = [(16, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_80386, 0...
(optable, optype, operand 0, operand 1, operand 2, CPU required, "opcodename", op0Register, op1Register, op2Register)
  tbl32_660F = [(16, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_80386,...
(optable, optype, operand 0, operand 1, operand 2, CPU required, "opcodename", op0Register, op1Register, op2Register)
  tbl32_F20F = [(16, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_80386,...
(optable, optype, operand 0, operand 1, operand 2, CPU required, "opcodename", op0Register, op1Register, op2Register)
  tbl32_F30F = [(16, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_80386,...
(optable, optype, operand 0, operand 1, operand 2, CPU required, "opcodename", op0Register, op1Register, op2Register)
  tbl32_0F00 = [(0, INS_SYSTEM, ADDRMETH_E | OPTYPE_w | OP_R, AR...
(optable, optype, operand 0, operand 1, operand 2, CPU required, "opcodename", op0Register, op1Register, op2Register)
  tbl32_0F01_00BF = [(0, INS_SYSTEM, ADDRMETH_M | OPTYPE_s | OP_...
  tbl32_0F01_rest = [(0, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, 0, ...
(optable, optype, operand 0, operand 1, operand 2, CPU required, "opcodename", op0Register, op1Register, op2Register)
  tbl32_0F18 = [(0, INS_SYSTEM, OP_W | ADDRMETH_M, ARG_NONE, ARG...
(optable, optype, operand 0, operand 1, operand 2, CPU required, "opcodename", op0Register, op1Register, op2Register)
  tbl32_0F38 = [(0, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, 0, 0, 0,...
  tbl32_660F38 = list(tbl32_0F38)
  tbl32_0F3A = [(0, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, 0, 0, 0,...
  tbl32_660F3A = list(tbl32_0F3A)
  tbl32_0F71 = [(0, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, 0, 0, 0,...
(optable, optype, operand 0, operand 1, operand 2, CPU required, "opcodename", op0Register, op1Register, op2Register)
  tbl32_0F72 = [(0, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, 0, 0, 0,...
(optable, optype, operand 0, operand 1, operand 2, CPU required, "opcodename", op0Register, op1Register, op2Register)
  tbl32_0F73 = [(0, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, 0, 0, 0,...
(optable, optype, operand 0, operand 1, operand 2, CPU required, "opcodename", op0Register, op1Register, op2Register)
  tbl32_660F73 = [(0, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, 0, 0, ...
(optable, optype, operand 0, operand 1, operand 2, CPU required, "opcodename", op0Register, op1Register, op2Register)
  tbl32_0FAE_00BF = [(0, INS_FPU, ADDRMETH_E | OPTYPE_v | OP_W, ...
(optable, optype, operand 0, operand 1, operand 2, CPU required, "opcodename", op0Register, op1Register, op2Register)
  tbl32_0FAE_rest = [(0, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, 0, ...
(optable, optype, operand 0, operand 1, operand 2, CPU required, "opcodename", op0Register, op1Register, op2Register)
  tbl32_0FBA = [(0, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, 0, 0, 0,...
(optable, optype, operand 0, operand 1, operand 2, CPU required, "opcodename", op0Register, op1Register, op2Register)
  tbl32_0FC2 = [(0, INS_XCHGCC, ADDRMETH_M | OPTYPE_q | OP_W, AR...
(optable, optype, operand 0, operand 1, operand 2, CPU required, "opcodename", op0Register, op1Register, op2Register)
  tbl32_0FC7_00BF = [(0, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, 0, ...
(optable, optype, operand 0, operand 1, operand 2, CPU required, "opcodename", op0Register, op1Register, op2Register)
  tbl32_0FC7_rest = [(0, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, 0, ...
(optable, optype, operand 0, operand 1, operand 2, CPU required, "opcodename", op0Register, op1Register, op2Register)
  tbl32_660FC7_00BF = [(0, INS_XCHGCC, ADDRMETH_M | OPTYPE_q | O...
(optable, optype, operand 0, operand 1, operand 2, CPU required, "opcodename", op0Register, op1Register, op2Register)
  tbl32_660FC7_rest = [(0, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, 0...
(optable, optype, operand 0, operand 1, operand 2, CPU required, "opcodename", op0Register, op1Register, op2Register)
  tbl32_F20FC7_00BF = [(0, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, 0...
(optable, optype, operand 0, operand 1, operand 2, CPU required, "opcodename", op0Register, op1Register, op2Register)
  tbl32_F20FC7_rest = [(0, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, 0...
(optable, optype, operand 0, operand 1, operand 2, CPU required, "opcodename", op0Register, op1Register, op2Register)
  tbl32_F30FC7_00BF = [(0, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, 0...
(optable, optype, operand 0, operand 1, operand 2, CPU required, "opcodename", op0Register, op1Register, op2Register)
  tbl32_F30FC7_rest = [(0, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, 0...
(optable, optype, operand 0, operand 1, operand 2, CPU required, "opcodename", op0Register, op1Register, op2Register)
  tbl32_80 = [(0, INS_ADD, ADDRMETH_E | OPTYPE_b | OP_W, ADDRMET...
(optable, optype, operand 0, operand 1, operand 2, CPU required, "opcodename", op0Register, op1Register, op2Register)
  tbl32_81 = [(0, INS_ADD, ADDRMETH_E | OPTYPE_v | OP_W, ADDRMET...
(optable, optype, operand 0, operand 1, operand 2, CPU required, "opcodename", op0Register, op1Register, op2Register)
  tbl32_82 = [(0, INS_ADD, ADDRMETH_E | OPTYPE_b | OP_W, ADDRMET...
(optable, optype, operand 0, operand 1, operand 2, CPU required, "opcodename", op0Register, op1Register, op2Register)
  tbl32_83 = [(0, INS_ADD, ADDRMETH_E | OPTYPE_v | OP_W, ADDRMET...
(optable, optype, operand 0, operand 1, operand 2, CPU required, "opcodename", op0Register, op1Register, op2Register)
  tbl32_C0 = [(0, INS_ROL, ADDRMETH_E | OPTYPE_b | OP_W, ADDRMET...
(optable, optype, operand 0, operand 1, operand 2, CPU required, "opcodename", op0Register, op1Register, op2Register)
  tbl32_C1 = [(0, INS_ROL, ADDRMETH_E | OPTYPE_v | OP_W, ADDRMET...
(optable, optype, operand 0, operand 1, operand 2, CPU required, "opcodename", op0Register, op1Register, op2Register)
  tbl32_D0 = [(0, INS_ROL, ADDRMETH_E | OPTYPE_b | OP_W, OP_IMM ...
(optable, optype, operand 0, operand 1, operand 2, CPU required, "opcodename", op0Register, op1Register, op2Register)
  tbl32_D1 = [(0, INS_ROL, ADDRMETH_E | OPTYPE_v | OP_W, OP_IMM ...
(optable, optype, operand 0, operand 1, operand 2, CPU required, "opcodename", op0Register, op1Register, op2Register)
  tbl32_D2 = [(0, INS_ROL, ADDRMETH_E | OPTYPE_b | OP_W, OP_REG ...
(optable, optype, operand 0, operand 1, operand 2, CPU required, "opcodename", op0Register, op1Register, op2Register)
  tbl32_D3 = [(0, INS_ROL, ADDRMETH_E | OPTYPE_v | OP_W, OP_REG ...
(optable, optype, operand 0, operand 1, operand 2, CPU required, "opcodename", op0Register, op1Register, op2Register)
  tbl32_F6 = [(0, INS_TEST, ADDRMETH_E | OPTYPE_b | OP_R, ADDRME...
(optable, optype, operand 0, operand 1, operand 2, CPU required, "opcodename", op0Register, op1Register, op2Register)
  tbl32_F7 = [(0, INS_TEST, ADDRMETH_E | OPTYPE_v | OP_R, ADDRME...
(optable, optype, operand 0, operand 1, operand 2, CPU required, "opcodename", op0Register, op1Register, op2Register)
  tbl32_FE = [(0, INS_INC, ADDRMETH_E | OPTYPE_b | OP_W, ARG_NON...
(optable, optype, operand 0, operand 1, operand 2, CPU required, "opcodename", op0Register, op1Register, op2Register)
  tbl32_FF = [(0, INS_INC, ADDRMETH_E | OPTYPE_v | OP_W, ARG_NON...
(optable, optype, operand 0, operand 1, operand 2, CPU required, "opcodename", op0Register, op1Register, op2Register)
  tbl32_fpuD8_00BF = [(0, INS_FPU, ADDRMETH_M | OPTYPE_fs | OP_W...
(optable, optype, operand 0, operand 1, operand 2, CPU required, "opcodename", op0Register, op1Register, op2Register)
  tbl32_fpuD8_rest = [(0, INS_FPU, OP_REG | OP_W, OP_REG | OP_R,...
(optable, optype, operand 0, operand 1, operand 2, CPU required, "opcodename", op0Register, op1Register, op2Register)
  tbl32_fpuD9_00BF = [(0, INS_FPU, ADDRMETH_M | OPTYPE_fs | OP_W...
(optable, optype, operand 0, operand 1, operand 2, CPU required, "opcodename", op0Register, op1Register, op2Register)
  tbl32_fpuD9_rest = [(0, INS_FPU, OP_REG | OP_W, OP_REG | OP_R,...
(optable, optype, operand 0, operand 1, operand 2, CPU required, "opcodename", op0Register, op1Register, op2Register)
  tbl32_fpuDA_00BF = [(0, INS_FPU, ADDRMETH_M | OPTYPE_d | OP_W,...
(optable, optype, operand 0, operand 1, operand 2, CPU required, "opcodename", op0Register, op1Register, op2Register)
  tbl32_fpuDA_rest = [(0, INS_FPU, OP_REG | OP_W, OP_REG | OP_R,...
(optable, optype, operand 0, operand 1, operand 2, CPU required, "opcodename", op0Register, op1Register, op2Register)
  tbl32_fpuDB_00BF = [(0, INS_FPU, ADDRMETH_M | OPTYPE_d | OP_W,...
(optable, optype, operand 0, operand 1, operand 2, CPU required, "opcodename", op0Register, op1Register, op2Register)
  tbl32_fpuDB_rest = [(0, INS_FPU, OP_REG | OP_W, OP_REG | OP_R,...
(optable, optype, operand 0, operand 1, operand 2, CPU required, "opcodename", op0Register, op1Register, op2Register)
  tbl32_fpuDC_00BF = [(0, INS_FPU, ADDRMETH_M | OPTYPE_fd | OP_W...
(optable, optype, operand 0, operand 1, operand 2, CPU required, "opcodename", op0Register, op1Register, op2Register)
  tbl32_fpuDC_rest = [(0, INS_FPU, OP_REG | OP_W, OP_REG | OP_R,...
(optable, optype, operand 0, operand 1, operand 2, CPU required, "opcodename", op0Register, op1Register, op2Register)
  tbl32_fpuDD_00BF = [(0, INS_FPU, ADDRMETH_M | OPTYPE_fd | OP_W...
(optable, optype, operand 0, operand 1, operand 2, CPU required, "opcodename", op0Register, op1Register, op2Register)
  tbl32_fpuDD_rest = [(0, INS_FPU, OP_REG | OP_W, ARG_NONE, ARG_...
(optable, optype, operand 0, operand 1, operand 2, CPU required, "opcodename", op0Register, op1Register, op2Register)
  tbl32_fpuDE_00BF = [(0, INS_FPU, ADDRMETH_M | OPTYPE_w | OP_W,...
(optable, optype, operand 0, operand 1, operand 2, CPU required, "opcodename", op0Register, op1Register, op2Register)
  tbl32_fpuDE_rest = [(0, INS_FPU, OP_REG | OP_W, OP_REG | OP_R,...
(optable, optype, operand 0, operand 1, operand 2, CPU required, "opcodename", op0Register, op1Register, op2Register)
  tbl32_fpuDF_00BF = [(0, INS_FPU, ADDRMETH_M | OPTYPE_w | OP_W,...
(optable, optype, operand 0, operand 1, operand 2, CPU required, "opcodename", op0Register, op1Register, op2Register)
  tbl32_fpuDF_rest = [(0, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_8...
  tbl_INVALID = [(0, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, 0, 0, 0...
These values allow an opcode to be sliced and diced to make it fit correctly into the current lookup table.
  tables86 = [(tbl32_Main, 0, 0xff, 0, 0xff), (tbl32_0F, 0, 0xff...
  regs = [("eax", "REG_GENERAL,REG_RET", 4), ("ecx", "REG_GENERA...
  prefix_table = {0xF0: PREFIX_LOCK, 0xF2: PREFIX_REPNZ, 0xF3: P...
Variables Details [hide private]

tbl32_Main

(optable, optype, operand 0, operand 1, operand 2, CPU required, "opcodename", op0Register, op1Register, op2Register)

Value:
[(0, INS_ADD, ADDRMETH_E | OPTYPE_b | OP_W, ADDRMETH_G | OPTYPE_b | OP\
_R, ARG_NONE, cpu_80386, "add", 0, 0, 0), (0, INS_ADD, ADDRMETH_E | OP\
TYPE_v | OP_W, ADDRMETH_G | OPTYPE_v | OP_R, ARG_NONE, cpu_80386, "add\
", 0, 0, 0), (0, INS_ADD, ADDRMETH_G | OPTYPE_b | OP_W, ADDRMETH_E | O\
PTYPE_b | OP_R, ARG_NONE, cpu_80386, "add", 0, 0, 0), (0, INS_ADD, ADD\
RMETH_G | OPTYPE_v | OP_W, ADDRMETH_E | OPTYPE_v | OP_R, ARG_NONE, cpu\
_80386, "add", 0, 0, 0), (0, INS_ADD, OP_REG | OP_W, ADDRMETH_I | OPTY\
PE_b | OP_SIGNED | OP_R, ARG_NONE, cpu_80386, "add", e_amd64_regs.REG_\
...

tbl32_0F

(optable, optype, operand 0, operand 1, operand 2, CPU required, "opcodename", op0Register, op1Register, op2Register)

Value:
[(16, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_80386, 0, 0, 0, 0), (17, 0,\
 ARG_NONE, ARG_NONE, ARG_NONE, cpu_80386, 0, 0, 0, 0), (0, INS_SYSTEM,\
 ADDRMETH_G | OPTYPE_v | OP_W, ADDRMETH_E | OPTYPE_w | OP_R, ARG_NONE,\
 cpu_80386, "lar", 0, 0, 0), (0, INS_SYSTEM, ADDRMETH_G | OPTYPE_v | O\
P_W, ADDRMETH_E | OPTYPE_w | OP_R, ARG_NONE, cpu_80386, "lsl", 0, 0, 0\
), (0, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, 0, 0, 0, 0), (0, INS_SYSTEM\
, ARG_NONE, ARG_NONE, ARG_NONE, cpu_AMD64, "syscall", 0, 0, 0), (0, IN\
S_SYSTEM, ARG_NONE, ARG_NONE, ARG_NONE, cpu_80386, "clts", 0, 0, 0), (\
...

tbl32_660F

(optable, optype, operand 0, operand 1, operand 2, CPU required, "opcodename", op0Register, op1Register, op2Register)

Value:
[(16, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_80386, 0, 0, 0, 0), (17, 0,\
 ARG_NONE, ARG_NONE, ARG_NONE, cpu_80386, 0, 0, 0, 0), (0, INS_SYSTEM,\
 ADDRMETH_G | OPTYPE_v | OP_W, ADDRMETH_E | OPTYPE_w | OP_R, ARG_NONE,\
 cpu_80386, "lar", 0, 0, 0), (0, INS_SYSTEM, ADDRMETH_G | OPTYPE_v | O\
P_W, ADDRMETH_E | OPTYPE_w | OP_R, ARG_NONE, cpu_80386, "lsl", 0, 0, 0\
), (0, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, 0, 0, 0, 0), (0, 0, ARG_NON\
E, ARG_NONE, ARG_NONE, 0, 0, 0, 0, 0), (0, INS_SYSTEM, ARG_NONE, ARG_N\
ONE, ARG_NONE, cpu_80386, "clts", 0, 0, 0), (0, 0, ARG_NONE, ARG_NONE,\
...

tbl32_F20F

(optable, optype, operand 0, operand 1, operand 2, CPU required, "opcodename", op0Register, op1Register, op2Register)

Value:
[(16, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_80386, 0, 0, 0, 0), (17, 0,\
 ARG_NONE, ARG_NONE, ARG_NONE, cpu_80386, 0, 0, 0, 0), (0, INS_SYSTEM,\
 ADDRMETH_G | OPTYPE_v | OP_W, ADDRMETH_E | OPTYPE_w | OP_R, ARG_NONE,\
 cpu_80386, "lar", 0, 0, 0), (0, INS_SYSTEM, ADDRMETH_G | OPTYPE_v | O\
P_W, ADDRMETH_E | OPTYPE_w | OP_R, ARG_NONE, cpu_80386, "lsl", 0, 0, 0\
), (0, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, 0, 0, 0, 0), (0, 0, ARG_NON\
E, ARG_NONE, ARG_NONE, 0, 0, 0, 0, 0), (0, INS_SYSTEM, ARG_NONE, ARG_N\
ONE, ARG_NONE, cpu_80386, "clts", 0, 0, 0), (0, 0, ARG_NONE, ARG_NONE,\
...

tbl32_F30F

(optable, optype, operand 0, operand 1, operand 2, CPU required, "opcodename", op0Register, op1Register, op2Register)

Value:
[(16, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_80386, 0, 0, 0, 0), (17, 0,\
 ARG_NONE, ARG_NONE, ARG_NONE, cpu_80386, 0, 0, 0, 0), (0, INS_SYSTEM,\
 ADDRMETH_G | OPTYPE_v | OP_W, ADDRMETH_E | OPTYPE_w | OP_R, ARG_NONE,\
 cpu_80386, "lar", 0, 0, 0), (0, INS_SYSTEM, ADDRMETH_G | OPTYPE_v | O\
P_W, ADDRMETH_E | OPTYPE_w | OP_R, ARG_NONE, cpu_80386, "lsl", 0, 0, 0\
), (0, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, 0, 0, 0, 0), (0, 0, ARG_NON\
E, ARG_NONE, ARG_NONE, 0, 0, 0, 0, 0), (0, INS_SYSTEM, ARG_NONE, ARG_N\
ONE, ARG_NONE, cpu_80386, "clts", 0, 0, 0), (0, 0, ARG_NONE, ARG_NONE,\
...

tbl32_0F00

(optable, optype, operand 0, operand 1, operand 2, CPU required, "opcodename", op0Register, op1Register, op2Register)

Value:
[(0, INS_SYSTEM, ADDRMETH_E | OPTYPE_w | OP_R, ARG_NONE, ARG_NONE, cpu\
_80386, "sldt", 0, 0, 0), (0, INS_SYSTEM, ADDRMETH_E | OPTYPE_w | OP_W\
, ARG_NONE, ARG_NONE, cpu_80386, "str", 0, 0, 0), (0, INS_SYSTEM, ADDR\
METH_E | OPTYPE_w | OP_W, ARG_NONE, ARG_NONE, cpu_80386, "lldt", 0, 0,\
 0), (0, INS_SYSTEM, ADDRMETH_E | OPTYPE_w | OP_W, ARG_NONE, ARG_NONE,\
 cpu_80386, "ltr", 0, 0, 0), (0, INS_SYSTEM, ADDRMETH_E | OPTYPE_w | O\
P_R, ARG_NONE, ARG_NONE, cpu_80386, "verr", 0, 0, 0), (0, INS_SYSTEM, \
ADDRMETH_E | OPTYPE_w | OP_R, ARG_NONE, ARG_NONE, cpu_80386, "verw", 0\
...

tbl32_0F01_00BF

Value:
[(0, INS_SYSTEM, ADDRMETH_M | OPTYPE_s | OP_R, ARG_NONE, ARG_NONE, cpu\
_80386, "sgdt", 0, 0, 0), (0, INS_SYSTEM, ADDRMETH_M | OPTYPE_s | OP_R\
, ARG_NONE, ARG_NONE, cpu_80386, "sidt", 0, 0, 0), (0, INS_SYSTEM, ADD\
RMETH_M | OPTYPE_s | OP_W, ARG_NONE, ARG_NONE, cpu_80386, "lgdt", 0, 0\
, 0), (0, INS_SYSTEM, ADDRMETH_M | OPTYPE_s | OP_W, ARG_NONE, ARG_NONE\
, cpu_80386, "lidt", 0, 0, 0), (0, INS_SYSTEM, ADDRMETH_E | OPTYPE_w |\
 OP_W, ARG_NONE, ARG_NONE, cpu_80386, "smsw", 0, 0, 0), (0, 0, ARG_NON\
E, ARG_NONE, ARG_NONE, 0, 0, 0, 0, 0), (0, INS_SYSTEM, ADDRMETH_E | OP\
...

tbl32_0F01_rest

(optable, optype, operand 0, operand 1, operand 2, CPU required, "opcodename", op0Register, op1Register, op2Register)

Value:
[(0, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, 0, 0, 0, 0), (0, INS_SYSTEM, \
ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM2, "vmcall", 0, 0, 0), (0, IN\
S_SYSTEM, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM2, "vmlaunch", 0, 0\
, 0), (0, INS_SYSTEM, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM2, "vmr\
esume", 0, 0, 0), (0, INS_SYSTEM, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PE\
NTIUM2, "vmxoff", 0, 0, 0), (0, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, 0,\
 0, 0, 0), (0, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, 0, 0, 0, 0), (0, 0,\
 ARG_NONE, ARG_NONE, ARG_NONE, 0, 0, 0, 0, 0), (0, INS_SYSTEM, ARG_NON\
...

tbl32_0F18

(optable, optype, operand 0, operand 1, operand 2, CPU required, "opcodename", op0Register, op1Register, op2Register)

Value:
[(0, INS_SYSTEM, OP_W | ADDRMETH_M, ARG_NONE, ARG_NONE, cpu_PENTIUM2, \
"prefetch", 0, 0, 0), (0, INS_SYSTEM, OP_REG | OP_W, ARG_NONE, ARG_NON\
E, cpu_PENTIUM2, "prefetch", e_amd64_regs.REG_TEST0, 0, 0), (0, INS_SY\
STEM, OP_REG | OP_W, ARG_NONE, ARG_NONE, cpu_PENTIUM2, "prefetch", e_a\
md64_regs.REG_TEST1, 0, 0), (0, INS_SYSTEM, OP_REG | OP_W, ARG_NONE, A\
RG_NONE, cpu_PENTIUM2, "prefetch", e_amd64_regs.REG_TEST2, 0, 0), (0, \
0, ARG_NONE, ARG_NONE, ARG_NONE, 0, 0, 0, 0, 0), (0, 0, ARG_NONE, ARG_\
NONE, ARG_NONE, 0, 0, 0, 0, 0), (0, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0\
...

tbl32_0F38

Value:
[(0, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, 0, 0, 0, 0) for x in xrange(2\
56)]

tbl32_0F3A

Value:
[(0, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, 0, 0, 0, 0) for x in xrange(2\
56)]

tbl32_0F71

(optable, optype, operand 0, operand 1, operand 2, CPU required, "opcodename", op0Register, op1Register, op2Register)

Value:
[(0, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, 0, 0, 0, 0), (0, 0, ARG_NONE,\
 ARG_NONE, ARG_NONE, 0, 0, 0, 0, 0), (0, INS_OTHER, ADDRMETH_N | OPTYP\
E_q | OP_W, ADDRMETH_I | OPTYPE_b | OP_R, ARG_NONE, cpu_PENTMMX, "psrl\
w", 0, 0, 0), (0, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, 0, 0, 0, 0), (0,\
 INS_OTHER, ADDRMETH_N | OPTYPE_q | OP_W, ADDRMETH_I | OPTYPE_b | OP_R\
, ARG_NONE, cpu_PENTMMX, "psraw", 0, 0, 0), (0, 0, ARG_NONE, ARG_NONE,\
 ARG_NONE, 0, 0, 0, 0, 0), (0, INS_OTHER, ADDRMETH_N | OPTYPE_q | OP_W\
, ADDRMETH_I | OPTYPE_b | OP_R, ARG_NONE, cpu_PENTMMX, "psllw", 0, 0, \
...

tbl32_0F72

(optable, optype, operand 0, operand 1, operand 2, CPU required, "opcodename", op0Register, op1Register, op2Register)

Value:
[(0, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, 0, 0, 0, 0), (0, 0, ARG_NONE,\
 ARG_NONE, ARG_NONE, 0, 0, 0, 0, 0), (0, INS_OTHER, ADDRMETH_N | OPTYP\
E_q | OP_W, ADDRMETH_I | OPTYPE_b | OP_R, ARG_NONE, cpu_PENTMMX, "psrl\
d", 0, 0, 0), (0, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, 0, 0, 0, 0), (0,\
 INS_OTHER, ADDRMETH_N | OPTYPE_q | OP_W, ADDRMETH_I | OPTYPE_b | OP_R\
, ARG_NONE, cpu_PENTMMX, "psrad", 0, 0, 0), (0, 0, ARG_NONE, ARG_NONE,\
 ARG_NONE, 0, 0, 0, 0, 0), (0, INS_OTHER, ADDRMETH_N | OPTYPE_q | OP_W\
, ADDRMETH_I | OPTYPE_b | OP_R, ARG_NONE, cpu_PENTMMX, "pslld", 0, 0, \
...

tbl32_0F73

(optable, optype, operand 0, operand 1, operand 2, CPU required, "opcodename", op0Register, op1Register, op2Register)

Value:
[(0, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, 0, 0, 0, 0), (0, 0, ARG_NONE,\
 ARG_NONE, ARG_NONE, 0, 0, 0, 0, 0), (0, INS_OTHER, ADDRMETH_N | OPTYP\
E_q | OP_W, ADDRMETH_I | OPTYPE_b | OP_R, ARG_NONE, cpu_PENTMMX, "psrl\
q", 0, 0, 0), (0, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, 0, 0, 0, 0), (0,\
 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, 0, 0, 0, 0), (0, 0, ARG_NONE, ARG\
_NONE, ARG_NONE, 0, 0, 0, 0, 0), (0, INS_OTHER, ADDRMETH_N | OPTYPE_q \
| OP_W, ADDRMETH_I | OPTYPE_b | OP_R, ARG_NONE, cpu_PENTMMX, "psllq", \
0, 0, 0), (0, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, 0, 0, 0, 0)]

tbl32_660F73

(optable, optype, operand 0, operand 1, operand 2, CPU required, "opcodename", op0Register, op1Register, op2Register)

Value:
[(0, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, 0, 0, 0, 0), (0, 0, ARG_NONE,\
 ARG_NONE, ARG_NONE, 0, 0, 0, 0, 0), (0, INS_OTHER, ADDRMETH_V | OPTYP\
E_dq | OP_W, ADDRMETH_I | OPTYPE_b | OP_R, ARG_NONE, cpu_PENTMMX, "psr\
lq", 0, 0, 0), (0, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, 0, 0, 0, 0), (0\
, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, 0, 0, 0, 0), (0, 0, ARG_NONE, AR\
G_NONE, ARG_NONE, 0, 0, 0, 0, 0), (0, INS_OTHER, ADDRMETH_V | OPTYPE_d\
q | OP_W, ADDRMETH_I | OPTYPE_b | OP_R, ARG_NONE, cpu_PENTMMX, "psllq"\
, 0, 0, 0), (0, INS_OTHER, ADDRMETH_V | OPTYPE_dq | OP_W, ADDRMETH_I |\
...

tbl32_0FAE_00BF

(optable, optype, operand 0, operand 1, operand 2, CPU required, "opcodename", op0Register, op1Register, op2Register)

Value:
[(0, INS_FPU, ADDRMETH_E | OPTYPE_v | OP_W, ARG_NONE, ARG_NONE, cpu_PE\
NTMMX, "fxsave", 0, 0, 0), (0, INS_FPU, ADDRMETH_E | OPTYPE_v | OP_R, \
ARG_NONE, ARG_NONE, cpu_PENTMMX, "fxrstor", 0, 0, 0), (0, INS_FPU, ADD\
RMETH_E | OPTYPE_v | OP_R, ARG_NONE, ARG_NONE, cpu_PENTIUM2, "ldmxcsr"\
, 0, 0, 0), (0, INS_FPU, ADDRMETH_E | OPTYPE_v | OP_W, ARG_NONE, ARG_N\
ONE, cpu_PENTIUM2, "stmxcsr", 0, 0, 0), (0, INS_FPU, ADDRMETH_E | OPTY\
PE_v | OP_W, ARG_NONE, ARG_NONE, cpu_AMD64, 'xsave', 0, 0, 0), (0, INS\
_FPU, ADDRMETH_E | OPTYPE_v | OP_W, ARG_NONE, ARG_NONE, cpu_AMD64, 'xr\
...

tbl32_0FAE_rest

(optable, optype, operand 0, operand 1, operand 2, CPU required, "opcodename", op0Register, op1Register, op2Register)

Value:
[(0, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, 0, 0, 0, 0), (0, 0, ARG_NONE,\
 ARG_NONE, ARG_NONE, 0, 0, 0, 0, 0), (0, 0, ARG_NONE, ARG_NONE, ARG_NO\
NE, 0, 0, 0, 0, 0), (0, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, 0, 0, 0, 0\
), (0, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, 0, 0, 0, 0), (0, INS_FPU, A\
RG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM2, "lfence", 0, 0, 0), (0, INS\
_FPU, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM2, "mfence", 0, 0, 0), \
(0, INS_FPU, ARG_NONE, ARG_NONE, ARG_NONE, cpu_PENTIUM2, "sfence", 0, \
0, 0)]

tbl32_0FBA

(optable, optype, operand 0, operand 1, operand 2, CPU required, "opcodename", op0Register, op1Register, op2Register)

Value:
[(0, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, 0, 0, 0, 0), (0, 0, ARG_NONE,\
 ARG_NONE, ARG_NONE, 0, 0, 0, 0, 0), (0, 0, ARG_NONE, ARG_NONE, ARG_NO\
NE, 0, 0, 0, 0, 0), (0, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, 0, 0, 0, 0\
), (0, INS_BITTEST, ADDRMETH_E | OPTYPE_v | OP_R, ADDRMETH_I | OPTYPE_\
b | OP_R, ARG_NONE, cpu_80386, "bt", 0, 0, 0), (0, INS_BITTEST, ADDRME\
TH_E | OPTYPE_v | OP_R, ADDRMETH_I | OPTYPE_b | OP_R, ARG_NONE, cpu_80\
386, "bts", 0, 0, 0), (0, INS_BITTEST, ADDRMETH_E | OPTYPE_v | OP_R, A\
DDRMETH_I | OPTYPE_b | OP_R, ARG_NONE, cpu_80386, "btr", 0, 0, 0), (0,\
...

tbl32_0FC2

(optable, optype, operand 0, operand 1, operand 2, CPU required, "opcodename", op0Register, op1Register, op2Register)

Value:
[(0, INS_XCHGCC, ADDRMETH_M | OPTYPE_q | OP_W, ARG_NONE, ARG_NONE, cpu\
_PENTIUM, "cmpxch8b", 0, 0, 0), (0, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0\
, 0, 0, 0, 0), (0, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, 0, 0, 0, 0), (0\
, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, 0, 0, 0, 0), (0, 0, ARG_NONE, AR\
G_NONE, ARG_NONE, 0, 0, 0, 0, 0), (0, 0, ARG_NONE, ARG_NONE, ARG_NONE,\
 0, 0, 0, 0, 0), (0, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, 0, 0, 0, 0), \
(0, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, 0, 0, 0, 0), (0, INS_SYSTEM, A\
DDRMETH_M | OPTYPE_q | OP_W, ARG_NONE, ARG_NONE, 0, "vmptrld", 0, 0, 0\
...

tbl32_0FC7_00BF

(optable, optype, operand 0, operand 1, operand 2, CPU required, "opcodename", op0Register, op1Register, op2Register)

Value:
[(0, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, 0, 0, 0, 0), (0, INS_XCHGCC, \
ADDRMETH_M | OPTYPE_q | OP_W, ARG_NONE, ARG_NONE, cpu_PENTIUM, "cmpxch\
8b", 0, 0, 0), (0, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, 0, 0, 0, 0), (0\
, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, 0, 0, 0, 0), (0, 0, ARG_NONE, AR\
G_NONE, ARG_NONE, 0, 0, 0, 0, 0), (0, 0, ARG_NONE, ARG_NONE, ARG_NONE,\
 0, 0, 0, 0, 0), (0, INS_SYSTEM, ADDRMETH_M | OPTYPE_q | OP_W, ARG_NON\
E, ARG_NONE, 0, "vmptrld", 0, 0, 0), (0, INS_SYSTEM, ADDRMETH_M | OPTY\
PE_q | OP_W, ARG_NONE, ARG_NONE, 0, "vmptrst", 0, 0, 0)]

tbl32_0FC7_rest

(optable, optype, operand 0, operand 1, operand 2, CPU required, "opcodename", op0Register, op1Register, op2Register)

Value:
[(0, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, 0, 0, 0, 0), (0, 0, ARG_NONE,\
 ARG_NONE, ARG_NONE, 0, 0, 0, 0, 0), (0, 0, ARG_NONE, ARG_NONE, ARG_NO\
NE, 0, 0, 0, 0, 0), (0, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, 0, 0, 0, 0\
), (0, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, 0, 0, 0, 0), (0, 0, ARG_NON\
E, ARG_NONE, ARG_NONE, 0, 0, 0, 0, 0), (0, 0, ARG_NONE, ARG_NONE, ARG_\
NONE, 0, 0, 0, 0, 0), (0, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, 0, 0, 0,\
 0), (0, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, 0, 0, 0, 0), (0, 0, ARG_N\
ONE, ARG_NONE, ARG_NONE, 0, 0, 0, 0, 0)]

tbl32_660FC7_00BF

(optable, optype, operand 0, operand 1, operand 2, CPU required, "opcodename", op0Register, op1Register, op2Register)

Value:
[(0, INS_XCHGCC, ADDRMETH_M | OPTYPE_q | OP_W, ARG_NONE, ARG_NONE, cpu\
_PENTIUM, "cmpxch8b", 0, 0, 0), (0, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0\
, 0, 0, 0, 0), (0, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, 0, 0, 0, 0), (0\
, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, 0, 0, 0, 0), (0, 0, ARG_NONE, AR\
G_NONE, ARG_NONE, 0, 0, 0, 0, 0), (0, 0, ARG_NONE, ARG_NONE, ARG_NONE,\
 0, 0, 0, 0, 0), (0, INS_SYSTEM, ADDRMETH_M | OPTYPE_q | OP_W, ARG_NON\
E, ARG_NONE, 0, "vmclear", 0, 0, 0), (0, INS_SYSTEM, ADDRMETH_M | OPTY\
PE_q | OP_W, ARG_NONE, ARG_NONE, 0, "vmptrst", 0, 0, 0)]

tbl32_660FC7_rest

(optable, optype, operand 0, operand 1, operand 2, CPU required, "opcodename", op0Register, op1Register, op2Register)

Value:
[(0, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, 0, 0, 0, 0), (0, 0, ARG_NONE,\
 ARG_NONE, ARG_NONE, 0, 0, 0, 0, 0), (0, 0, ARG_NONE, ARG_NONE, ARG_NO\
NE, 0, 0, 0, 0, 0), (0, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, 0, 0, 0, 0\
), (0, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, 0, 0, 0, 0), (0, 0, ARG_NON\
E, ARG_NONE, ARG_NONE, 0, 0, 0, 0, 0), (0, 0, ARG_NONE, ARG_NONE, ARG_\
NONE, 0, 0, 0, 0, 0), (0, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, 0, 0, 0,\
 0), (0, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, 0, 0, 0, 0), (0, 0, ARG_N\
ONE, ARG_NONE, ARG_NONE, 0, 0, 0, 0, 0)]

tbl32_F20FC7_00BF

(optable, optype, operand 0, operand 1, operand 2, CPU required, "opcodename", op0Register, op1Register, op2Register)

Value:
[(0, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, 0, 0, 0, 0), (0, 0, ARG_NONE,\
 ARG_NONE, ARG_NONE, 0, 0, 0, 0, 0), (0, 0, ARG_NONE, ARG_NONE, ARG_NO\
NE, 0, 0, 0, 0, 0), (0, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, 0, 0, 0, 0\
), (0, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, 0, 0, 0, 0), (0, 0, ARG_NON\
E, ARG_NONE, ARG_NONE, 0, 0, 0, 0, 0), (0, 0, ARG_NONE, ARG_NONE, ARG_\
NONE, 0, 0, 0, 0, 0), (0, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, 0, 0, 0,\
 0)]

tbl32_F20FC7_rest

(optable, optype, operand 0, operand 1, operand 2, CPU required, "opcodename", op0Register, op1Register, op2Register)

Value:
[(0, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, 0, 0, 0, 0), (0, 0, ARG_NONE,\
 ARG_NONE, ARG_NONE, 0, 0, 0, 0, 0), (0, 0, ARG_NONE, ARG_NONE, ARG_NO\
NE, 0, 0, 0, 0, 0), (0, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, 0, 0, 0, 0\
), (0, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, 0, 0, 0, 0), (0, 0, ARG_NON\
E, ARG_NONE, ARG_NONE, 0, 0, 0, 0, 0), (0, 0, ARG_NONE, ARG_NONE, ARG_\
NONE, 0, 0, 0, 0, 0), (0, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, 0, 0, 0,\
 0), (0, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, 0, 0, 0, 0), (0, 0, ARG_N\
ONE, ARG_NONE, ARG_NONE, 0, 0, 0, 0, 0)]

tbl32_F30FC7_00BF

(optable, optype, operand 0, operand 1, operand 2, CPU required, "opcodename", op0Register, op1Register, op2Register)

Value:
[(0, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, 0, 0, 0, 0), (0, 0, ARG_NONE,\
 ARG_NONE, ARG_NONE, 0, 0, 0, 0, 0), (0, 0, ARG_NONE, ARG_NONE, ARG_NO\
NE, 0, 0, 0, 0, 0), (0, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, 0, 0, 0, 0\
), (0, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, 0, 0, 0, 0), (0, 0, ARG_NON\
E, ARG_NONE, ARG_NONE, 0, 0, 0, 0, 0), (0, INS_SYSTEM, ADDRMETH_M | OP\
TYPE_q | OP_W, ARG_NONE, ARG_NONE, 0, "vmxon", 0, 0, 0), (0, 0, ARG_NO\
NE, ARG_NONE, ARG_NONE, 0, 0, 0, 0, 0)]

tbl32_F30FC7_rest

(optable, optype, operand 0, operand 1, operand 2, CPU required, "opcodename", op0Register, op1Register, op2Register)

Value:
[(0, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, 0, 0, 0, 0), (0, 0, ARG_NONE,\
 ARG_NONE, ARG_NONE, 0, 0, 0, 0, 0), (0, 0, ARG_NONE, ARG_NONE, ARG_NO\
NE, 0, 0, 0, 0, 0), (0, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, 0, 0, 0, 0\
), (0, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, 0, 0, 0, 0), (0, 0, ARG_NON\
E, ARG_NONE, ARG_NONE, 0, 0, 0, 0, 0), (0, 0, ARG_NONE, ARG_NONE, ARG_\
NONE, 0, 0, 0, 0, 0), (0, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, 0, 0, 0,\
 0), (0, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, 0, 0, 0, 0), (0, 0, ARG_N\
ONE, ARG_NONE, ARG_NONE, 0, 0, 0, 0, 0)]

tbl32_80

(optable, optype, operand 0, operand 1, operand 2, CPU required, "opcodename", op0Register, op1Register, op2Register)

Value:
[(0, INS_ADD, ADDRMETH_E | OPTYPE_b | OP_W, ADDRMETH_I | OPTYPE_b | OP\
_SIGNED | OP_R, ARG_NONE, cpu_80386, "add", 0, 0, 0), (0, INS_OR, ADDR\
METH_E | OPTYPE_b | OP_W, ADDRMETH_I | OPTYPE_b | OP_SIGNED | OP_R, AR\
G_NONE, cpu_80386, "or", 0, 0, 0), (0, INS_ADD, ADDRMETH_E | OPTYPE_b \
| OP_W, ADDRMETH_I | OPTYPE_b | OP_SIGNED | OP_R, ARG_NONE, cpu_80386,\
 "adc", 0, 0, 0), (0, INS_SUB, ADDRMETH_E | OPTYPE_b | OP_W, ADDRMETH_\
I | OPTYPE_b | OP_SIGNED | OP_R, ARG_NONE, cpu_80386, "sbb", 0, 0, 0),\
 (0, INS_AND, ADDRMETH_E | OPTYPE_b | OP_W, ADDRMETH_I | OPTYPE_b | OP\
...

tbl32_81

(optable, optype, operand 0, operand 1, operand 2, CPU required, "opcodename", op0Register, op1Register, op2Register)

Value:
[(0, INS_ADD, ADDRMETH_E | OPTYPE_v | OP_W, ADDRMETH_I | OPTYPE_z | OP\
_SIGNED | OP_R, ARG_NONE, cpu_80386, "add", 0, 0, 0), (0, INS_OR, ADDR\
METH_E | OPTYPE_v | OP_W, ADDRMETH_I | OPTYPE_z | OP_SIGNED | OP_R, AR\
G_NONE, cpu_80386, "or", 0, 0, 0), (0, INS_ADD, ADDRMETH_E | OPTYPE_v \
| OP_W, ADDRMETH_I | OPTYPE_z | OP_SIGNED | OP_R, ARG_NONE, cpu_80386,\
 "adc", 0, 0, 0), (0, INS_SUB, ADDRMETH_E | OPTYPE_v | OP_W, ADDRMETH_\
I | OPTYPE_z | OP_SIGNED | OP_R, ARG_NONE, cpu_80386, "sbb", 0, 0, 0),\
 (0, INS_AND, ADDRMETH_E | OPTYPE_v | OP_W, ADDRMETH_I | OPTYPE_z | OP\
...

tbl32_82

(optable, optype, operand 0, operand 1, operand 2, CPU required, "opcodename", op0Register, op1Register, op2Register)

Value:
[(0, INS_ADD, ADDRMETH_E | OPTYPE_b | OP_W, ADDRMETH_I | OPTYPE_b | OP\
_SIGNED | OP_R, ARG_NONE, cpu_80386, "add", 0, 0, 0), (0, INS_OR, ADDR\
METH_E | OPTYPE_b | OP_W, ADDRMETH_I | OPTYPE_b | OP_SIGNED | OP_R, AR\
G_NONE, cpu_80386, "or", 0, 0, 0), (0, INS_ADD, ADDRMETH_E | OPTYPE_b \
| OP_W, ADDRMETH_I | OPTYPE_b | OP_SIGNED | OP_R, ARG_NONE, cpu_80386,\
 "adc", 0, 0, 0), (0, INS_SUB, ADDRMETH_E | OPTYPE_b | OP_W, ADDRMETH_\
I | OPTYPE_b | OP_SIGNED | OP_R, ARG_NONE, cpu_80386, "sbb", 0, 0, 0),\
 (0, INS_AND, ADDRMETH_E | OPTYPE_b | OP_W, ADDRMETH_I | OPTYPE_b | OP\
...

tbl32_83

(optable, optype, operand 0, operand 1, operand 2, CPU required, "opcodename", op0Register, op1Register, op2Register)

Value:
[(0, INS_ADD, ADDRMETH_E | OPTYPE_v | OP_W, ADDRMETH_I | OPTYPE_b | OP\
_SIGNED | OP_R, ARG_NONE, cpu_80386, "add", 0, 0, 0), (0, INS_OR, ADDR\
METH_E | OPTYPE_v | OP_W, ADDRMETH_I | OPTYPE_b | OP_SIGNED | OP_R, AR\
G_NONE, cpu_80386, "or", 0, 0, 0), (0, INS_ADD, ADDRMETH_E | OPTYPE_v \
| OP_W, ADDRMETH_I | OPTYPE_b | OP_SIGNED | OP_R, ARG_NONE, cpu_80386,\
 "adc", 0, 0, 0), (0, INS_SUB, ADDRMETH_E | OPTYPE_v | OP_W, ADDRMETH_\
I | OPTYPE_b | OP_SIGNED | OP_R, ARG_NONE, cpu_80386, "sbb", 0, 0, 0),\
 (0, INS_AND, ADDRMETH_E | OPTYPE_v | OP_W, ADDRMETH_I | OPTYPE_b | OP\
...

tbl32_C0

(optable, optype, operand 0, operand 1, operand 2, CPU required, "opcodename", op0Register, op1Register, op2Register)

Value:
[(0, INS_ROL, ADDRMETH_E | OPTYPE_b | OP_W, ADDRMETH_I | OPTYPE_b | OP\
_R, ARG_NONE, cpu_80386, "rol", 0, 0, 0), (0, INS_ROR, ADDRMETH_E | OP\
TYPE_b | OP_W, ADDRMETH_I | OPTYPE_b | OP_R, ARG_NONE, cpu_80386, "ror\
", 0, 0, 0), (0, INS_ROL, ADDRMETH_E | OPTYPE_b | OP_W, ADDRMETH_I | O\
PTYPE_b | OP_R, ARG_NONE, cpu_80386, "rcl", 0, 0, 0), (0, INS_ROR, ADD\
RMETH_E | OPTYPE_b | OP_W, ADDRMETH_I | OPTYPE_b | OP_R, ARG_NONE, cpu\
_80386, "rcr", 0, 0, 0), (0, INS_SHL, ADDRMETH_E | OPTYPE_b | OP_W, AD\
DRMETH_I | OPTYPE_b | OP_R, ARG_NONE, cpu_80386, "shl", 0, 0, 0), (0, \
...

tbl32_C1

(optable, optype, operand 0, operand 1, operand 2, CPU required, "opcodename", op0Register, op1Register, op2Register)

Value:
[(0, INS_ROL, ADDRMETH_E | OPTYPE_v | OP_W, ADDRMETH_I | OPTYPE_b | OP\
_R, ARG_NONE, cpu_80386, "rol", 0, 0, 0), (0, INS_ROR, ADDRMETH_E | OP\
TYPE_v | OP_W, ADDRMETH_I | OPTYPE_b | OP_R, ARG_NONE, cpu_80386, "ror\
", 0, 0, 0), (0, INS_ROL, ADDRMETH_E | OPTYPE_v | OP_W, ADDRMETH_I | O\
PTYPE_b | OP_R, ARG_NONE, cpu_80386, "rcl", 0, 0, 0), (0, INS_ROR, ADD\
RMETH_E | OPTYPE_v | OP_W, ADDRMETH_I | OPTYPE_b | OP_R, ARG_NONE, cpu\
_80386, "rcr", 0, 0, 0), (0, INS_SHL, ADDRMETH_E | OPTYPE_v | OP_W, AD\
DRMETH_I | OPTYPE_b | OP_R, ARG_NONE, cpu_80386, "shl", 0, 0, 0), (0, \
...

tbl32_D0

(optable, optype, operand 0, operand 1, operand 2, CPU required, "opcodename", op0Register, op1Register, op2Register)

Value:
[(0, INS_ROL, ADDRMETH_E | OPTYPE_b | OP_W, OP_IMM | OP_R, ARG_NONE, c\
pu_80386, "rol", 0, 1, 0), (0, INS_ROR, ADDRMETH_E | OPTYPE_b | OP_W, \
OP_IMM | OP_R, ARG_NONE, cpu_80386, "ror", 0, 1, 0), (0, INS_ROL, ADDR\
METH_E | OPTYPE_b | OP_W, OP_IMM | OP_R, ARG_NONE, cpu_80386, "rcl", 0\
, 1, 0), (0, INS_ROR, ADDRMETH_E | OPTYPE_b | OP_W, OP_IMM | OP_R, ARG\
_NONE, cpu_80386, "rcr", 0, 1, 0), (0, INS_SHL, ADDRMETH_E | OPTYPE_b \
| OP_W, OP_IMM | OP_R, ARG_NONE, cpu_80386, "shl", 0, 1, 0), (0, INS_S\
HR, ADDRMETH_E | OPTYPE_b | OP_W, OP_IMM | OP_R, ARG_NONE, cpu_80386, \
...

tbl32_D1

(optable, optype, operand 0, operand 1, operand 2, CPU required, "opcodename", op0Register, op1Register, op2Register)

Value:
[(0, INS_ROL, ADDRMETH_E | OPTYPE_v | OP_W, OP_IMM | OP_R, ARG_NONE, c\
pu_80386, "rol", 0, 1, 0), (0, INS_ROR, ADDRMETH_E | OPTYPE_v | OP_W, \
OP_IMM | OP_R, ARG_NONE, cpu_80386, "ror", 0, 1, 0), (0, INS_ROL, ADDR\
METH_E | OPTYPE_v | OP_W, OP_IMM | OP_R, ARG_NONE, cpu_80386, "rcl", 0\
, 1, 0), (0, INS_ROR, ADDRMETH_E | OPTYPE_v | OP_W, OP_IMM | OP_R, ARG\
_NONE, cpu_80386, "rcr", 0, 1, 0), (0, INS_SHL, ADDRMETH_E | OPTYPE_v \
| OP_W, OP_IMM | OP_R, ARG_NONE, cpu_80386, "shl", 0, 1, 0), (0, INS_S\
HR, ADDRMETH_E | OPTYPE_v | OP_W, OP_IMM | OP_R, ARG_NONE, cpu_80386, \
...

tbl32_D2

(optable, optype, operand 0, operand 1, operand 2, CPU required, "opcodename", op0Register, op1Register, op2Register)

Value:
[(0, INS_ROL, ADDRMETH_E | OPTYPE_b | OP_W, OP_REG | OP_R, ARG_NONE, c\
pu_80386, "rol", 0, e_amd64_regs.REG_CL, 0), (0, INS_ROR, ADDRMETH_E |\
 OPTYPE_b | OP_W, OP_REG | OP_R, ARG_NONE, cpu_80386, "ror", 0, e_amd6\
4_regs.REG_CL, 0), (0, INS_ROL, ADDRMETH_E | OPTYPE_b | OP_W, OP_REG |\
 OP_R, ARG_NONE, cpu_80386, "rcl", 0, e_amd64_regs.REG_CL, 0), (0, INS\
_ROR, ADDRMETH_E | OPTYPE_b | OP_W, OP_REG | OP_R, ARG_NONE, cpu_80386\
, "rcr", 0, e_amd64_regs.REG_CL, 0), (0, INS_SHL, ADDRMETH_E | OPTYPE_\
b | OP_W, OP_REG | OP_R, ARG_NONE, cpu_80386, "shl", 0, e_amd64_regs.R\
...

tbl32_D3

(optable, optype, operand 0, operand 1, operand 2, CPU required, "opcodename", op0Register, op1Register, op2Register)

Value:
[(0, INS_ROL, ADDRMETH_E | OPTYPE_v | OP_W, OP_REG | OP_R, ARG_NONE, c\
pu_80386, "rol", 0, e_amd64_regs.REG_CL, 0), (0, INS_ROR, ADDRMETH_E |\
 OPTYPE_v | OP_W, OP_REG | OP_R, ARG_NONE, cpu_80386, "ror", 0, e_amd6\
4_regs.REG_CL, 0), (0, INS_ROL, ADDRMETH_E | OPTYPE_v | OP_W, OP_REG |\
 OP_R, ARG_NONE, cpu_80386, "rcl", 0, e_amd64_regs.REG_CL, 0), (0, INS\
_ROR, ADDRMETH_E | OPTYPE_v | OP_W, OP_REG | OP_R, ARG_NONE, cpu_80386\
, "rcr", 0, e_amd64_regs.REG_CL, 0), (0, INS_SHL, ADDRMETH_E | OPTYPE_\
v | OP_W, OP_REG | OP_R, ARG_NONE, cpu_80386, "shl", 0, e_amd64_regs.R\
...

tbl32_F6

(optable, optype, operand 0, operand 1, operand 2, CPU required, "opcodename", op0Register, op1Register, op2Register)

Value:
[(0, INS_TEST, ADDRMETH_E | OPTYPE_b | OP_R, ADDRMETH_I | OPTYPE_b | O\
P_SIGNED | OP_R, ARG_NONE, cpu_80386, "test", 0, 0, 0), (0, INS_TEST, \
ADDRMETH_E | OPTYPE_b | OP_R, ADDRMETH_I | OPTYPE_b | OP_SIGNED | OP_R\
, ARG_NONE, cpu_80386, "test", 0, 0, 0), (0, INS_NOT, ADDRMETH_E | OPT\
YPE_b | OP_W, ARG_NONE, ARG_NONE, cpu_80386, "not", 0, 0, 0), (0, INS_\
NEG, ADDRMETH_E | OPTYPE_b | OP_W, ARG_NONE, ARG_NONE, cpu_80386, "neg\
", 0, 0, 0), (0, INS_MUL, OP_REG | OP_W, ADDRMETH_E | OPTYPE_b | OP_R,\
 ARG_NONE, cpu_80386, "mul", e_amd64_regs.REG_AL, 0, 0), (0, INS_MUL, \
...

tbl32_F7

(optable, optype, operand 0, operand 1, operand 2, CPU required, "opcodename", op0Register, op1Register, op2Register)

Value:
[(0, INS_TEST, ADDRMETH_E | OPTYPE_v | OP_R, ADDRMETH_I | OPTYPE_z | O\
P_R, ARG_NONE, cpu_80386, "test", 0, 0, 0), (0, 0, ARG_NONE, ARG_NONE,\
 ARG_NONE, 0, 0, 0, 0, 0), (0, INS_NOT, ADDRMETH_E | OPTYPE_v | OP_W, \
ARG_NONE, ARG_NONE, cpu_80386, "not", 0, 0, 0), (0, INS_NEG, ADDRMETH_\
E | OPTYPE_v | OP_W, ARG_NONE, ARG_NONE, cpu_80386, "neg", 0, 0, 0), (\
0, INS_MUL, OP_REG | OP_W, ADDRMETH_E | OPTYPE_v | OP_R, ARG_NONE, cpu\
_80386, "mul", e_amd64_regs.REG_EAX, 0, 0), (0, INS_MUL, OP_REG | OP_W\
, ADDRMETH_E | OPTYPE_v | OP_R, ARG_NONE, cpu_80386, "imul", e_amd64_r\
...

tbl32_FE

(optable, optype, operand 0, operand 1, operand 2, CPU required, "opcodename", op0Register, op1Register, op2Register)

Value:
[(0, INS_INC, ADDRMETH_E | OPTYPE_b | OP_W, ARG_NONE, ARG_NONE, cpu_80\
386, "inc", 0, 0, 0), (0, INS_DEC, ADDRMETH_E | OPTYPE_b | OP_W, ARG_N\
ONE, ARG_NONE, cpu_80386, "dec", 0, 0, 0), (0, 0, ARG_NONE, ARG_NONE, \
ARG_NONE, 0, 0, 0, 0, 0), (0, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, 0, 0\
, 0, 0), (0, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, 0, 0, 0, 0), (0, 0, A\
RG_NONE, ARG_NONE, ARG_NONE, 0, 0, 0, 0, 0), (0, 0, ARG_NONE, ARG_NONE\
, ARG_NONE, 0, 0, 0, 0, 0), (0, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, 0,\
 0, 0, 0)]

tbl32_FF

(optable, optype, operand 0, operand 1, operand 2, CPU required, "opcodename", op0Register, op1Register, op2Register)

Value:
[(0, INS_INC, ADDRMETH_E | OPTYPE_v | OP_W, ARG_NONE, ARG_NONE, cpu_80\
386, "inc", 0, 0, 0), (0, INS_DEC, ADDRMETH_E | OPTYPE_v | OP_W, ARG_N\
ONE, ARG_NONE, cpu_80386, "dec", 0, 0, 0), (0, INS_CALL, ADDRMETH_E | \
OPTYPE_v | OP_X | OP_64AUTO, ARG_NONE, ARG_NONE, cpu_80386, "call", 0,\
 0, 0), (0, INS_CALL, ADDRMETH_E | OPTYPE_p | OP_X, ARG_NONE, ARG_NONE\
, cpu_80386, "call", 0, 0, 0), (0, INS_BRANCH, ADDRMETH_E | OPTYPE_v |\
 OP_X | OP_64AUTO, ARG_NONE, ARG_NONE, cpu_80386, "jmp", 0, 0, 0), (0,\
 INS_BRANCH, ADDRMETH_E | OPTYPE_p | OP_X, ARG_NONE, ARG_NONE, cpu_803\
...

tbl32_fpuD8_00BF

(optable, optype, operand 0, operand 1, operand 2, CPU required, "opcodename", op0Register, op1Register, op2Register)

Value:
[(0, INS_FPU, ADDRMETH_M | OPTYPE_fs | OP_W, ARG_NONE, ARG_NONE, cpu_8\
0387, "fadd", 0, 0, 0), (0, INS_FPU, ADDRMETH_M | OPTYPE_fs | OP_W, AR\
G_NONE, ARG_NONE, cpu_80387, "fmul", 0, 0, 0), (0, INS_FPU, ADDRMETH_M\
 | OPTYPE_fs | OP_W, ARG_NONE, ARG_NONE, cpu_80387, "fcom", 0, 0, 0), \
(0, INS_FPU, ADDRMETH_M | OPTYPE_fs | OP_W, ARG_NONE, ARG_NONE, cpu_80\
387, "fcomp", 0, 0, 0), (0, INS_FPU, ADDRMETH_M | OPTYPE_fs | OP_W, AR\
G_NONE, ARG_NONE, cpu_80387, "fsub", 0, 0, 0), (0, INS_FPU, ADDRMETH_M\
 | OPTYPE_fs | OP_W, ARG_NONE, ARG_NONE, cpu_80387, "fsubr", 0, 0, 0),\
...

tbl32_fpuD8_rest

(optable, optype, operand 0, operand 1, operand 2, CPU required, "opcodename", op0Register, op1Register, op2Register)

Value:
[(0, INS_FPU, OP_REG | OP_W, OP_REG | OP_R, ARG_NONE, cpu_80387, "fadd\
", e_amd64_regs.REG_ST0, e_amd64_regs.REG_ST0, 0), (0, INS_FPU, OP_REG\
 | OP_W, OP_REG | OP_R, ARG_NONE, cpu_80387, "fadd", e_amd64_regs.REG_\
ST0, e_amd64_regs.REG_ST1, 0), (0, INS_FPU, OP_REG | OP_W, OP_REG | OP\
_R, ARG_NONE, cpu_80387, "fadd", e_amd64_regs.REG_ST0, e_amd64_regs.RE\
G_ST2, 0), (0, INS_FPU, OP_REG | OP_W, OP_REG | OP_R, ARG_NONE, cpu_80\
387, "fadd", e_amd64_regs.REG_ST0, e_amd64_regs.REG_ST3, 0), (0, INS_F\
PU, OP_REG | OP_W, OP_REG | OP_R, ARG_NONE, cpu_80387, "fadd", e_amd64\
...

tbl32_fpuD9_00BF

(optable, optype, operand 0, operand 1, operand 2, CPU required, "opcodename", op0Register, op1Register, op2Register)

Value:
[(0, INS_FPU, ADDRMETH_M | OPTYPE_fs | OP_W, ARG_NONE, ARG_NONE, cpu_8\
0387, "fld", 0, 0, 0), (0, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_80387,\
 0, 0, 0, 0), (0, INS_FPU, ADDRMETH_M | OPTYPE_fs | OP_W, ARG_NONE, AR\
G_NONE, cpu_80387, "fst", 0, 0, 0), (0, INS_FPU, ADDRMETH_M | OPTYPE_f\
s | OP_W, ARG_NONE, ARG_NONE, cpu_80387, "fstp", 0, 0, 0), (0, INS_FPU\
, ADDRMETH_M | OPTYPE_fv | OP_W, ARG_NONE, ARG_NONE, cpu_80387, "flden\
v", 0, 0, 0), (0, INS_FPU, ADDRMETH_M | OPTYPE_w | OP_W, ARG_NONE, ARG\
_NONE, cpu_80387, "fldcw", 0, 0, 0), (0, INS_FPU, ADDRMETH_M | OPTYPE_\
...

tbl32_fpuD9_rest

(optable, optype, operand 0, operand 1, operand 2, CPU required, "opcodename", op0Register, op1Register, op2Register)

Value:
[(0, INS_FPU, OP_REG | OP_W, OP_REG | OP_R, ARG_NONE, cpu_80387, "fld"\
, e_amd64_regs.REG_ST0, e_amd64_regs.REG_ST0, 0), (0, INS_FPU, OP_REG \
| OP_W, OP_REG | OP_R, ARG_NONE, cpu_80387, "fld", e_amd64_regs.REG_ST\
0, e_amd64_regs.REG_ST1, 0), (0, INS_FPU, OP_REG | OP_W, OP_REG | OP_R\
, ARG_NONE, cpu_80387, "fld", e_amd64_regs.REG_ST0, e_amd64_regs.REG_S\
T2, 0), (0, INS_FPU, OP_REG | OP_W, OP_REG | OP_R, ARG_NONE, cpu_80387\
, "fld", e_amd64_regs.REG_ST0, e_amd64_regs.REG_ST3, 0), (0, INS_FPU, \
OP_REG | OP_W, OP_REG | OP_R, ARG_NONE, cpu_80387, "fld", e_amd64_regs\
...

tbl32_fpuDA_00BF

(optable, optype, operand 0, operand 1, operand 2, CPU required, "opcodename", op0Register, op1Register, op2Register)

Value:
[(0, INS_FPU, ADDRMETH_M | OPTYPE_d | OP_W, ARG_NONE, ARG_NONE, cpu_80\
387, "fiadd", 0, 0, 0), (0, INS_FPU, ADDRMETH_M | OPTYPE_d | OP_W, ARG\
_NONE, ARG_NONE, cpu_80387, "fimul", 0, 0, 0), (0, INS_FPU, ADDRMETH_M\
 | OPTYPE_d | OP_W, ARG_NONE, ARG_NONE, cpu_80387, "ficom", 0, 0, 0), \
(0, INS_FPU, ADDRMETH_M | OPTYPE_d | OP_W, ARG_NONE, ARG_NONE, cpu_803\
87, "ficomp", 0, 0, 0), (0, INS_FPU, ADDRMETH_M | OPTYPE_d | OP_W, ARG\
_NONE, ARG_NONE, cpu_80387, "fisub", 0, 0, 0), (0, INS_FPU, ADDRMETH_M\
 | OPTYPE_d | OP_W, ARG_NONE, ARG_NONE, cpu_80387, "fisubr", 0, 0, 0),\
...

tbl32_fpuDA_rest

(optable, optype, operand 0, operand 1, operand 2, CPU required, "opcodename", op0Register, op1Register, op2Register)

Value:
[(0, INS_FPU, OP_REG | OP_W, OP_REG | OP_R, ARG_NONE, cpu_80387, "fcmo\
vb", e_amd64_regs.REG_ST0, e_amd64_regs.REG_ST0, 0), (0, INS_FPU, OP_R\
EG | OP_W, OP_REG | OP_R, ARG_NONE, cpu_80387, "fcmovb", e_amd64_regs.\
REG_ST0, e_amd64_regs.REG_ST1, 0), (0, INS_FPU, OP_REG | OP_W, OP_REG \
| OP_R, ARG_NONE, cpu_80387, "fcmovb", e_amd64_regs.REG_ST0, e_amd64_r\
egs.REG_ST2, 0), (0, INS_FPU, OP_REG | OP_W, OP_REG | OP_R, ARG_NONE, \
cpu_80387, "fcmovb", e_amd64_regs.REG_ST0, e_amd64_regs.REG_ST3, 0), (\
0, INS_FPU, OP_REG | OP_W, OP_REG | OP_R, ARG_NONE, cpu_80387, "fcmovb\
...

tbl32_fpuDB_00BF

(optable, optype, operand 0, operand 1, operand 2, CPU required, "opcodename", op0Register, op1Register, op2Register)

Value:
[(0, INS_FPU, ADDRMETH_M | OPTYPE_d | OP_W, ARG_NONE, ARG_NONE, cpu_80\
387, "fild", 0, 0, 0), (0, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_80387,\
 0, 0, 0, 0), (0, INS_FPU, ADDRMETH_M | OPTYPE_d | OP_W, ARG_NONE, ARG\
_NONE, cpu_80387, "fist", 0, 0, 0), (0, INS_FPU, ADDRMETH_M | OPTYPE_d\
 | OP_W, ARG_NONE, ARG_NONE, cpu_80387, "fistp", 0, 0, 0), (0, 0, ARG_\
NONE, ARG_NONE, ARG_NONE, cpu_80387, 0, 0, 0, 0), (0, INS_FPU, ADDRMET\
H_M | OPTYPE_fe | OP_W, ARG_NONE, ARG_NONE, cpu_80387, "fld", 0, 0, 0)\
, (0, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_80387, 0, 0, 0, 0), (0, INS\
...

tbl32_fpuDB_rest

(optable, optype, operand 0, operand 1, operand 2, CPU required, "opcodename", op0Register, op1Register, op2Register)

Value:
[(0, INS_FPU, OP_REG | OP_W, OP_REG | OP_R, ARG_NONE, cpu_80387, "fcmo\
vnb", e_amd64_regs.REG_ST0, e_amd64_regs.REG_ST0, 0), (0, INS_FPU, OP_\
REG | OP_W, OP_REG | OP_R, ARG_NONE, cpu_80387, "fcmovnb", e_amd64_reg\
s.REG_ST0, e_amd64_regs.REG_ST1, 0), (0, INS_FPU, OP_REG | OP_W, OP_RE\
G | OP_R, ARG_NONE, cpu_80387, "fcmovnb", e_amd64_regs.REG_ST0, e_amd6\
4_regs.REG_ST2, 0), (0, INS_FPU, OP_REG | OP_W, OP_REG | OP_R, ARG_NON\
E, cpu_80387, "fcmovnb", e_amd64_regs.REG_ST0, e_amd64_regs.REG_ST3, 0\
), (0, INS_FPU, OP_REG | OP_W, OP_REG | OP_R, ARG_NONE, cpu_80387, "fc\
...

tbl32_fpuDC_00BF

(optable, optype, operand 0, operand 1, operand 2, CPU required, "opcodename", op0Register, op1Register, op2Register)

Value:
[(0, INS_FPU, ADDRMETH_M | OPTYPE_fd | OP_W, ARG_NONE, ARG_NONE, cpu_8\
0387, "fadd", 0, 0, 0), (0, INS_FPU, ADDRMETH_M | OPTYPE_fd | OP_W, AR\
G_NONE, ARG_NONE, cpu_80387, "fmul", 0, 0, 0), (0, INS_FPU, ADDRMETH_M\
 | OPTYPE_fd | OP_W, ARG_NONE, ARG_NONE, cpu_80387, "fcom", 0, 0, 0), \
(0, INS_FPU, ADDRMETH_M | OPTYPE_fd | OP_W, ARG_NONE, ARG_NONE, cpu_80\
387, "fcomp", 0, 0, 0), (0, INS_FPU, ADDRMETH_M | OPTYPE_fd | OP_W, AR\
G_NONE, ARG_NONE, cpu_80387, "fsub", 0, 0, 0), (0, INS_FPU, ADDRMETH_M\
 | OPTYPE_fd | OP_W, ARG_NONE, ARG_NONE, cpu_80387, "fsubr", 0, 0, 0),\
...

tbl32_fpuDC_rest

(optable, optype, operand 0, operand 1, operand 2, CPU required, "opcodename", op0Register, op1Register, op2Register)

Value:
[(0, INS_FPU, OP_REG | OP_W, OP_REG | OP_R, ARG_NONE, cpu_80387, "fadd\
", e_amd64_regs.REG_ST0, e_amd64_regs.REG_ST0, 0), (0, INS_FPU, OP_REG\
 | OP_W, OP_REG | OP_R, ARG_NONE, cpu_80387, "fadd", e_amd64_regs.REG_\
ST1, e_amd64_regs.REG_ST0, 0), (0, INS_FPU, OP_REG | OP_W, OP_REG | OP\
_R, ARG_NONE, cpu_80387, "fadd", e_amd64_regs.REG_ST2, e_amd64_regs.RE\
G_ST0, 0), (0, INS_FPU, OP_REG | OP_W, OP_REG | OP_R, ARG_NONE, cpu_80\
387, "fadd", e_amd64_regs.REG_ST3, e_amd64_regs.REG_ST0, 0), (0, INS_F\
PU, OP_REG | OP_W, OP_REG | OP_R, ARG_NONE, cpu_80387, "fadd", e_amd64\
...

tbl32_fpuDD_00BF

(optable, optype, operand 0, operand 1, operand 2, CPU required, "opcodename", op0Register, op1Register, op2Register)

Value:
[(0, INS_FPU, ADDRMETH_M | OPTYPE_fd | OP_W, ARG_NONE, ARG_NONE, cpu_8\
0387, "fld", 0, 0, 0), (0, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_80387,\
 0, 0, 0, 0), (0, INS_FPU, ADDRMETH_M | OPTYPE_fd | OP_W, ARG_NONE, AR\
G_NONE, cpu_80387, "fst", 0, 0, 0), (0, INS_FPU, ADDRMETH_M | OPTYPE_f\
d | OP_W, ARG_NONE, ARG_NONE, cpu_80387, "fstp", 0, 0, 0), (0, INS_FPU\
, ADDRMETH_M | OPTYPE_fv | OP_W, ARG_NONE, ARG_NONE, cpu_80387, "frsto\
r", 0, 0, 0), (0, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_80387, 0, 0, 0,\
 0), (0, INS_FPU, ADDRMETH_M | OPTYPE_fv | OP_W, ARG_NONE, ARG_NONE, c\
...

tbl32_fpuDD_rest

(optable, optype, operand 0, operand 1, operand 2, CPU required, "opcodename", op0Register, op1Register, op2Register)

Value:
[(0, INS_FPU, OP_REG | OP_W, ARG_NONE, ARG_NONE, cpu_80387, "ffree", e\
_amd64_regs.REG_ST0, 0, 0), (0, INS_FPU, OP_REG | OP_W, ARG_NONE, ARG_\
NONE, cpu_80387, "ffree", e_amd64_regs.REG_ST1, 0, 0), (0, INS_FPU, OP\
_REG | OP_W, ARG_NONE, ARG_NONE, cpu_80387, "ffree", e_amd64_regs.REG_\
ST2, 0, 0), (0, INS_FPU, OP_REG | OP_W, ARG_NONE, ARG_NONE, cpu_80387,\
 "ffree", e_amd64_regs.REG_ST3, 0, 0), (0, INS_FPU, OP_REG | OP_W, ARG\
_NONE, ARG_NONE, cpu_80387, "ffree", e_amd64_regs.REG_ST4, 0, 0), (0, \
INS_FPU, OP_REG | OP_W, ARG_NONE, ARG_NONE, cpu_80387, "ffree", e_amd6\
...

tbl32_fpuDE_00BF

(optable, optype, operand 0, operand 1, operand 2, CPU required, "opcodename", op0Register, op1Register, op2Register)

Value:
[(0, INS_FPU, ADDRMETH_M | OPTYPE_w | OP_W, ARG_NONE, ARG_NONE, cpu_80\
387, "fiadd", 0, 0, 0), (0, INS_FPU, ADDRMETH_M | OPTYPE_w | OP_W, ARG\
_NONE, ARG_NONE, cpu_80387, "fimul", 0, 0, 0), (0, INS_FPU, ADDRMETH_M\
 | OPTYPE_w | OP_W, ARG_NONE, ARG_NONE, cpu_80387, "ficom", 0, 0, 0), \
(0, INS_FPU, ADDRMETH_M | OPTYPE_w | OP_W, ARG_NONE, ARG_NONE, cpu_803\
87, "ficomp", 0, 0, 0), (0, INS_FPU, ADDRMETH_M | OPTYPE_w | OP_W, ARG\
_NONE, ARG_NONE, cpu_80387, "fisub", 0, 0, 0), (0, INS_FPU, ADDRMETH_M\
 | OPTYPE_w | OP_W, ARG_NONE, ARG_NONE, cpu_80387, "fisubr", 0, 0, 0),\
...

tbl32_fpuDE_rest

(optable, optype, operand 0, operand 1, operand 2, CPU required, "opcodename", op0Register, op1Register, op2Register)

Value:
[(0, INS_FPU, OP_REG | OP_W, OP_REG | OP_R, ARG_NONE, cpu_80387, "fadd\
p", e_amd64_regs.REG_ST0, e_amd64_regs.REG_ST0, 0), (0, INS_FPU, OP_RE\
G | OP_W, OP_REG | OP_R, ARG_NONE, cpu_80387, "faddp", e_amd64_regs.RE\
G_ST1, e_amd64_regs.REG_ST0, 0), (0, INS_FPU, OP_REG | OP_W, OP_REG | \
OP_R, ARG_NONE, cpu_80387, "faddp", e_amd64_regs.REG_ST2, e_amd64_regs\
.REG_ST0, 0), (0, INS_FPU, OP_REG | OP_W, OP_REG | OP_R, ARG_NONE, cpu\
_80387, "faddp", e_amd64_regs.REG_ST3, e_amd64_regs.REG_ST0, 0), (0, I\
NS_FPU, OP_REG | OP_W, OP_REG | OP_R, ARG_NONE, cpu_80387, "faddp", e_\
...

tbl32_fpuDF_00BF

(optable, optype, operand 0, operand 1, operand 2, CPU required, "opcodename", op0Register, op1Register, op2Register)

Value:
[(0, INS_FPU, ADDRMETH_M | OPTYPE_w | OP_W, ARG_NONE, ARG_NONE, cpu_80\
387, "fild", 0, 0, 0), (0, INS_FPU, ADDRMETH_M | OPTYPE_w | OP_W, ARG_\
NONE, ARG_NONE, cpu_80387, "fisttp", 0, 0, 0), (0, INS_FPU, ADDRMETH_M\
 | OPTYPE_w | OP_W, ARG_NONE, ARG_NONE, cpu_80387, "fist", 0, 0, 0), (\
0, INS_FPU, ADDRMETH_M | OPTYPE_w | OP_W, ARG_NONE, ARG_NONE, cpu_8038\
7, "fistp", 0, 0, 0), (0, INS_FPU, ADDRMETH_M | OPTYPE_fb | OP_W, ARG_\
NONE, ARG_NONE, cpu_80387, "fbld", 0, 0, 0), (0, INS_FPU, ADDRMETH_M |\
 OPTYPE_q | OP_W, ARG_NONE, ARG_NONE, cpu_80387, "fild", 0, 0, 0), (0,\
...

tbl32_fpuDF_rest

Value:
[(0, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_80387, 0, 0, 0, 0), (0, 0, A\
RG_NONE, ARG_NONE, ARG_NONE, cpu_80387, 0, 0, 0, 0), (0, 0, ARG_NONE, \
ARG_NONE, ARG_NONE, cpu_80387, 0, 0, 0, 0), (0, 0, ARG_NONE, ARG_NONE,\
 ARG_NONE, cpu_80387, 0, 0, 0, 0), (0, 0, ARG_NONE, ARG_NONE, ARG_NONE\
, cpu_80387, 0, 0, 0, 0), (0, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_803\
87, 0, 0, 0, 0), (0, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_80387, 0, 0,\
 0, 0), (0, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_80387, 0, 0, 0, 0), (\
0, 0, ARG_NONE, ARG_NONE, ARG_NONE, cpu_80387, 0, 0, 0, 0), (0, 0, ARG\
...

tbl_INVALID


These values allow an opcode to be sliced and diced to make it fit correctly into the current lookup table.

    (tbl32_0F, 0, 0xff, 0, 0xff),
    (tbl32_80, 3, 0x07, 0, 0xff, 4),

           Table pointer
           shift bits right        (eg.  >> 4 makes each line in the table valid for 16 
                                    numbers... ie 0xc0-0xcf are all one entry in the table)
           mask part of the byte   (eg.  & 0x7 only makes use of the 00000111 bits...)
           simple subtraction
           highest acceptable value
           tables86 entry to handle the falloff (from the previous check)

IMPORTANT: the decoder will assume the opcode is ultimately selected by bits in a MOD/RM 
    byte if the field in tabdesc[2] != 0xff

Value:
[(0, 0, ARG_NONE, ARG_NONE, ARG_NONE, 0, 0, 0, 0, 0)]

tables86

Value:
[(tbl32_Main, 0, 0xff, 0, 0xff), (tbl32_0F, 0, 0xff, 0, 0xff), (tbl32_\
80, 3, 0x07, 0, 0xff), (tbl32_81, 3, 0x07, 0, 0xff), (tbl32_82, 3, 0x0\
7, 0, 0xff), (tbl32_83, 3, 0x07, 0, 0xff), (tbl32_C0, 3, 0x07, 0, 0xff\
), (tbl32_C1, 3, 0x07, 0, 0xff), (tbl32_D0, 3, 0x07, 0, 0xff), (tbl32_\
D1, 3, 0x07, 0, 0xff), (tbl32_D2, 3, 0x07, 0, 0xff), (tbl32_D3, 3, 0x0\
7, 0, 0xff), (tbl32_F6, 3, 0x07, 0, 0xff), (tbl32_F7, 3, 0x07, 0, 0xff\
), (tbl32_FE, 3, 0x07, 0, 0xff), (tbl32_FF, 3, 0x07, 0, 0xff), (tbl32_\
0F00, 3, 0x07, 0, 0xff), (tbl32_0F01_00BF, 3, 0x07, 0, 0xbf, 42), (tbl\
...

regs

Value:
[("eax", "REG_GENERAL,REG_RET", 4), ("ecx", "REG_GENERAL,REG_COUNT", 4\
), ("edx", "REG_GENERAL", 4), ("ebx", "REG_GENERAL", 4), ("esp", "REG_\
SP", 4), ("ebp", "REG_GENERAL,REG_FP", 4), ("esi", "REG_GENERAL,REG_SR\
C", 4), ("edi", "REG_GENERAL,REG_DEST", 4), ("ax", "REG_GENERAL,REG_RE\
T", 2), ("cx", "REG_GENERAL,REG_COUNT", 2), ("dx", "REG_GENERAL", 2), \
("bx", "REG_GENERAL", 2), ("sp", "REG_SP", 2), ("bp", "REG_GENERAL,REG\
_FP", 2), ("si", "REG_GENERAL,REG_SRC", 2), ("di", "REG_GENERAL,REG_DE\
ST", 2), ("al", "REG_GENERAL", 1), ("cl", "REG_GENERAL", 1), ("dl", "R\
...

prefix_table

Value:
{0xF0: PREFIX_LOCK, 0xF2: PREFIX_REPNZ, 0xF3: PREFIX_REP, 0x2E: PREFIX\
_CS, 0x36: PREFIX_SS, 0x3E: PREFIX_DS, 0x26: PREFIX_ES, 0x64: PREFIX_F\
S, 0x65: PREFIX_GS, 0x66: PREFIX_OP_SIZE, 0x67: PREFIX_ADDR_SIZE, 0: 0\
}